SPI_DEVICE/2P Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.277m	679.333ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.560s	130.723us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.010s	96.899us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.600s	2.896ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.190s	908.177us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.520s	630.692us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.010s	96.899us	20	20	100.00
		spi_device_csr_aliasing	24.190s	908.177us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.230s	35.730us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.590s	135.278us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.360s	16.239us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.640s	53.864us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	2.020s	14.784us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.820s	319.680us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.820s	319.680us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	28.390s	7.018ms	50	50	100.00
		spi_device_tpm_sts_read	2.670s	124.986us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	37.530s	5.440ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	40.540s	24.440ms	50	50	100.00
		spi_device_flash_all	3.994m	35.629ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	30.470s	6.519ms	50	50	100.00
		spi_device_flash_all	3.994m	35.629ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	30.470s	6.519ms	50	50	100.00
		spi_device_flash_all	3.994m	35.629ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	3.994m	35.629ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.480s	2.309ms	50	50	100.00
		spi_device_flash_all	3.994m	35.629ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.480s	2.309ms	50	50	100.00
		spi_device_flash_all	3.994m	35.629ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.480s	2.309ms	50	50	100.00
		spi_device_flash_all	3.994m	35.629ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.480s	2.309ms	50	50	100.00
		spi_device_flash_all	3.994m	35.629ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.480s	2.309ms	50	50	100.00
		spi_device_flash_all	3.994m	35.629ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	27.860s	7.461ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.936m	26.811ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.936m	26.811ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.936m	26.811ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.257m	24.258ms	50	50	100.00
		spi_device_read_buffer_direct	21.580s	7.414ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.936m	26.811ms	50	50	100.00
		spi_device_flash_all	3.994m	35.629ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	3.994m	35.629ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	3.994m	35.629ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	15.200s	2.158ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	15.200s	2.158ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.277m	679.333ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.721m	46.523ms	50	50	100.00
V2	stress_all	spi_device_stress_all	8.635m	64.479ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.360s	75.236us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.300s	34.933us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.490s	1.123ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.490s	1.123ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.560s	130.723us	5	5	100.00
		spi_device_csr_rw	4.010s	96.899us	20	20	100.00
		spi_device_csr_aliasing	24.190s	908.177us	5	5	100.00
		spi_device_same_csr_outstanding	5.370s	1.911ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.560s	130.723us	5	5	100.00
		spi_device_csr_rw	4.010s	96.899us	20	20	100.00
		spi_device_csr_aliasing	24.190s	908.177us	5	5	100.00
		spi_device_same_csr_outstanding	5.370s	1.911ms	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.580s	136.238us	5	5	100.00
		spi_device_tl_intg_err	20.910s	3.438ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.910s	3.438ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.675m	303.591ms	50	50	100.00
		TOTAL			1151	1151	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.34	99.18	96.61	74.78	89.36	98.49	95.74	99.26