SPI_HOST Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.283m	12.195ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	20.210us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	15.216us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	164.473us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	41.870us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	24.907us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	15.216us	20	20	100.00
		spi_host_csr_aliasing	5.000s	41.870us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	14.711us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	21.690us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	5.000s	21.183us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	29.000s	444.718us	50	50	100.00
		spi_host_error_cmd	5.000s	55.615us	50	50	100.00
		spi_host_event	19.167m	137.299ms	50	50	100.00
V2	clock_rate	spi_host_speed	36.000s	10.033ms	49	50	98.00
V2	speed	spi_host_speed	36.000s	10.033ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	36.000s	10.033ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	54.000s	1.717ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	132.658us	50	50	100.00
V2	cpol_cpha	spi_host_speed	36.000s	10.033ms	49	50	98.00
V2	full_cycle	spi_host_speed	36.000s	10.033ms	49	50	98.00
V2	duplex	spi_host_smoke	2.283m	12.195ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.283m	12.195ms	50	50	100.00
V2	stress_all	spi_host_stress_all	2.583m	18.632ms	50	50	100.00
V2	spien	spi_host_spien	40.000s	3.617ms	50	50	100.00
V2	stall	spi_host_status_stall	52.083m	1.000s	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	28.000s	9.479ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	29.000s	444.718us	50	50	100.00
V2	alert_test	spi_host_alert_test	5.000s	27.785us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	21.751us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	132.298us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	132.298us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	20.210us	5	5	100.00
		spi_host_csr_rw	5.000s	15.216us	20	20	100.00
		spi_host_csr_aliasing	5.000s	41.870us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	25.087us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	20.210us	5	5	100.00
		spi_host_csr_rw	5.000s	15.216us	20	20	100.00
		spi_host_csr_aliasing	5.000s	41.870us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	25.087us	20	20	100.00
V2		TOTAL			687	690	99.57
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	82.462us	20	20	100.00
		spi_host_sec_cm	5.000s	126.043us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	82.462us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	9.700m	46.014ms	10	10	100.00
		TOTAL			837	840	99.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.20	96.78	93.27	98.69	94.36	73.07	100.00	97.29	90.42

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

14.spi_host_status_stall.107215620627185536723828224069518818538937988896223991352023306260300217646137
Line 1973, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/14.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 5609655982 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 5609655982 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=5609656000 ps
  UVM_INFO @ 5609655982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 31.spi_host_status_stall.104797421773711783934884108362956439985940878901098753477939368474452682260025
    Line 18179, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/31.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:
- Test spi_host_speed has 1 failures.
  - 32.spi_host_speed.32064392371996548637994453921203313925026974579402173627088871911323269495993
    Line 260, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/32.spi_host_speed/latest/run.log
```
  UVM_FATAL @ 10032574851 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x9f387654, Comparison=CompareOpEq, exp_data=0x0, call_count=54
  UVM_INFO @ 10032574851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```