SRAM_CTRL/MAIN Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.712m	1.310ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.060s	31.169us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.220s	43.215us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	4.020s	1.372ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.080s	14.152us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.400s	1.365ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.220s	43.215us	20	20	100.00
		sram_ctrl_csr_aliasing	2.080s	14.152us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.535m	42.196ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.883m	23.219ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	21.500m	26.784ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.175m	10.673ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	42.571m	1.004s	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.581m	76.686ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.887m	88.303ms	50	50	100.00
V2	executable	sram_ctrl_executable	21.657m	118.014ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.051m	2.816ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.797m	84.453ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.750m	1.501ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.911m	3.130ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.837m	1.335ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.913m	19.840ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.660s	4.808ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.167h	353.424ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.170s	14.540us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.860s	1.168ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.860s	1.168ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.060s	31.169us	5	5	100.00
		sram_ctrl_csr_rw	2.220s	43.215us	20	20	100.00
		sram_ctrl_csr_aliasing	2.080s	14.152us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.400s	40.768us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.060s	31.169us	5	5	100.00
		sram_ctrl_csr_rw	2.220s	43.215us	20	20	100.00
		sram_ctrl_csr_aliasing	2.080s	14.152us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.400s	40.768us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.098m	30.687ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.030s	7.977us	0	5	0.00
		sram_ctrl_tl_intg_err	3.990s	190.655us	19	20	95.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.030s	7.977us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.990s	190.655us	19	20	95.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.913m	19.840ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.913m	19.840ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.220s	43.215us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.657m	118.014ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.657m	118.014ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.657m	118.014ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.887m	88.303ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	11.270s	4.691ms	39	50	78.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.098m	30.687ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	12.780s	7.353ms	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.712m	1.310ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.712m	1.310ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.657m	118.014ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.030s	7.977us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.887m	88.303ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.030s	7.977us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.030s	7.977us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.712m	1.310ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.030s	7.977us	0	5	0.00
V2S		TOTAL			117	145	80.69
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.587m	8.373ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1162	1190	97.65

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.11	93.01	85.18	100.00	98.03	98.61	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 11 failures:
- Test sram_ctrl_readback_err has 11 failures.
  - 3.sram_ctrl_readback_err.54238757020286163984112578241335685286657959732167237557908175635419500367894
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 676062082 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5f) != exp (0x7a)
  UVM_INFO @ 676062082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 18.sram_ctrl_readback_err.93904891375958247773178171719746788119255173113288118687993184443861970972713
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/18.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 2830121073 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x40) != exp (0x66)
  UVM_INFO @ 2830121073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
Offending 'reqfifo_rvalid' has 10 failures:
- Test sram_ctrl_mubi_enc_err has 10 failures.
  - 7.sram_ctrl_mubi_enc_err.45759697968747466405780871988660859500628689793007964817586216156535003341222
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 1370281344 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 1370281344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.sram_ctrl_mubi_enc_err.41969191837510531163185665842330353333869153226833046500105882342615379231075
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/9.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 2640007977 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 2640007977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

Test sram_ctrl_sec_cm has 2 failures.

0.sram_ctrl_sec_cm.98482337786032689127619921274522186668703456707419361960839067671726675861036
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   7977462 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   7977462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.sram_ctrl_sec_cm.45201094348830215528527042661370503179330592149306839112559065350505567630642
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @  11702512 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  11702512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(depth_o <= *'(Depth))' has 2 failures:

Test sram_ctrl_sec_cm has 2 failures.

1.sram_ctrl_sec_cm.63151768340216461844472676384673367211026427136788312750692676337079484719908
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @   2925823 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @   2925823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.sram_ctrl_sec_cm.57513349210943360536081123052499936444695554015700721583098421177327428182517
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @   3253733 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @   3253733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending 'pend_req[d2h.d_source].pend' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 2.sram_ctrl_sec_cm.111774644669916640900789262650894278115911190073997677031231919498715508713215
    Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
      Offending 'pend_req[d2h.d_source].pend'
  UVM_ERROR @   4025601 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
  UVM_INFO @   4025601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4941) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_mubi_enc_err has 1 failures.

4.sram_ctrl_mubi_enc_err.7435770266280405999529941068250529164929059095939240951115017143298042808090
Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_mubi_enc_err/latest/run.log

  UVM_ERROR @ 659431634 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4941) { a_addr: 'hadaf9974  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd8  a_opcode: 'h4  a_user: 'h25baa  d_param: 'h0  d_source: 'hd8  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 659431634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_tl_intg_err has 1 failures.
  - 17.sram_ctrl_tl_intg_err.20354493673328437267537792166697495425315925362105260211278165877514435758157
    Line 130, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 777400427 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 777400427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```