SRAM_CTRL/RET Simulation Results

Sunday June 08 2025 00:08:59 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.467m	1.362ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.200s	13.921us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.180s	96.588us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.770s	173.977us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.180s	17.194us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.670s	210.484us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.180s	96.588us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	17.194us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.770s	673.938us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.920s	182.730us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	22.137m	89.674ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.284m	16.809ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.563m	66.876ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	22.096m	5.009ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	16.910s	4.368ms	50	50	100.00
V2	executable	sram_ctrl_executable	22.348m	102.984ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.436m	1.227ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.011m	99.306ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.664m	283.630us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.666m	601.068us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.610m	1.261ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	18.978m	58.418ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.320s	209.534us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.007h	58.715ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.240s	15.929us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.460s	248.909us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.460s	248.909us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.200s	13.921us	5	5	100.00
		sram_ctrl_csr_rw	2.180s	96.588us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	17.194us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.250s	172.073us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.200s	13.921us	5	5	100.00
		sram_ctrl_csr_rw	2.180s	96.588us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	17.194us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.250s	172.073us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.500s	3.247ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.150s	12.731us	0	5	0.00
		sram_ctrl_tl_intg_err	5.070s	803.777us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.150s	12.731us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	5.070s	803.777us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	18.978m	58.418ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	18.978m	58.418ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.180s	96.588us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	22.348m	102.984ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	22.348m	102.984ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	22.348m	102.984ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	16.910s	4.368ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.750s	50.823us	47	50	94.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.500s	3.247ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.760s	387.964us	35	50	70.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.467m	1.362ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.467m	1.362ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	22.348m	102.984ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.150s	12.731us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	16.910s	4.368ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.150s	12.731us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.150s	12.731us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.467m	1.362ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.150s	12.731us	0	5	0.00
V2S		TOTAL			122	145	84.14
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.447m	3.422ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1165	1190	97.90

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	99.07	93.01	85.10	100.00	97.99	98.60	98.14

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 15 failures:

  • Test sram_ctrl_readback_err has 15 failures.

    • 6.sram_ctrl_readback_err.48484617645670370522678460512335465699157495190919908466157417511530325768843
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/6.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 186469883 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7) != exp (0x5b)
        UVM_INFO @ 186469883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_readback_err.35190294862445845237506818581175252375474372818770357733664345346124815388101
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  46291887 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x18) != exp (0x73)
        UVM_INFO @  46291887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 13 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 2.sram_ctrl_sec_cm.20356619669403587986001305741206981709644897318209081757349716933132515764126
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2623276 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2623276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.28586725453595900226870977682404889089496601281894488496701159954514426807656
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  12731242 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  12731242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending 'reqfifo_rvalid' has 3 failures:

  • Test sram_ctrl_mubi_enc_err has 3 failures.

    • 39.sram_ctrl_mubi_enc_err.47171438354651070887236344667268627515859044209709584596811154229007717461521
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  40212159 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  40212159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 42.sram_ctrl_mubi_enc_err.106564218026733411675098182932529487445146307504792861504841138519952185150768
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 130305271 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 130305271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.98817727909891404684998611471240711259918010290645123060249934820868948116482
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   4300619 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   4300619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.114563102374351288791963230316964622610814449693644929359368679998144249534742
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @  15849019 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @  15849019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 6.sram_ctrl_csr_mem_rw_with_rand_reset.83018177738531124083036375154876037788445709584547613126195182460389148675737
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 137950149 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
        UVM_INFO @ 137950149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:832) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 19.sram_ctrl_csr_mem_rw_with_rand_reset.73768935773677249626467972827207013522451645550982725863930976018550953195131
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  45937901 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @  45937901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---