ADC_CTRL Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: `c4214fe`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	21.960s	5.709ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	6.260s	1.148ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	3.900s	503.815us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.934m	26.848ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	9.050s	1.010ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	4.210s	528.231us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	3.900s	503.815us	20	20	100.00
		adc_ctrl_csr_aliasing	9.050s	1.010ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	21.443m	487.996ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	18.034m	488.647ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	23.575m	490.289ms	48	50	96.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.352m	497.618ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	20.674m	539.984ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	27.111m	590.046ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.129m	575.789ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	20.870m	520.943ms	34	50	68.00
V2	poweron_counter	adc_ctrl_poweron_counter	21.850s	5.336ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.528m	45.024ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	5.233m	117.487ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	50.192m	10.000s	46	50	92.00
V2	alert_test	adc_ctrl_alert_test	3.620s	450.753us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.770s	443.237us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.710s	655.355us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.710s	655.355us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	6.260s	1.148ms	5	5	100.00
		adc_ctrl_csr_rw	3.900s	503.815us	20	20	100.00
		adc_ctrl_csr_aliasing	9.050s	1.010ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	28.110s	4.344ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	6.260s	1.148ms	5	5	100.00
		adc_ctrl_csr_rw	3.900s	503.815us	20	20	100.00
		adc_ctrl_csr_aliasing	9.050s	1.010ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	28.110s	4.344ms	20	20	100.00
V2		TOTAL			716	740	96.76
V2S	tl_intg_err	adc_ctrl_sec_cm	24.110s	7.275ms	5	5	100.00
		adc_ctrl_tl_intg_err	30.290s	8.365ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	30.290s	8.365ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	56.613m	10.000s	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			891	920	96.85

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.44	99.05	96.03	100.00	100.00	98.64	97.57	90.81

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 20 failures:

Test adc_ctrl_filters_both has 2 failures.

5.adc_ctrl_filters_both.111807611424220867835712915128018090219131315272192785792626557562799015228527
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.adc_ctrl_filters_both.40297969212308788899291215912528139162316883292378053712529954861324306804505
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all_with_rand_reset has 4 failures.

6.adc_ctrl_stress_all_with_rand_reset.70644209559627895184342066842832455840342513246611050126172717257839090816997
Line 169, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.adc_ctrl_stress_all_with_rand_reset.56495987650221140111991013346312040564119725966674916741205593727932440107598
Line 159, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test adc_ctrl_clock_gating has 11 failures.

8.adc_ctrl_clock_gating.40423225659550024273276407732753074312794458321346893755001247304469884526298
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.adc_ctrl_clock_gating.27027659761892723368197726984536694095954812767894870117468534164176785905807
Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test adc_ctrl_stress_all has 3 failures.

25.adc_ctrl_stress_all.5262337625221207101241825874348402020816617694664127058170978816272790596232
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.adc_ctrl_stress_all.86403095822296726025854795815678675241458727153329776768453157199310074343214
Line 167, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 6 failures:

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
- 21.adc_ctrl_stress_all_with_rand_reset.50306430054034340947415658618228726823932849406319783580327775646388262652413
  Line 152, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6532827175 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 6532827175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test adc_ctrl_clock_gating has 4 failures.

22.adc_ctrl_clock_gating.110527805750519103740943163988722846942503750223926308325951907948788286465248
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 2328427578 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 2328427578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.adc_ctrl_clock_gating.47557745142366269158159732950208345637296773748626716791055323581883181738322
Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 186998530597 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 186998530597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test adc_ctrl_stress_all has 1 failures.

33.adc_ctrl_stress_all.90934821715152269322948543969839500450014978657551570477349697018661531665978
Line 147, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 18809619957 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 18809619957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 3 failures:

Test adc_ctrl_filters_interrupt has 2 failures.

2.adc_ctrl_filters_interrupt.19570102326000972465072908343577106567947130588235833656067889948638705203409
Line 162, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 328217129467 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 328217129467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.adc_ctrl_filters_interrupt.76401594459721084482988086065510133682563217072699674582307000743395643219526
Line 162, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 245871876790 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 245871876790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_clock_gating has 1 failures.

19.adc_ctrl_clock_gating.39182330125997279305165503352195631499219195011537362499713857627648628667930
Line 180, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 483441172802 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 483441172802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---