AES/MASKED Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: `c4214fe`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	59.722us	1	1	100.00
V1	smoke	aes_smoke	8.000s	373.507us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	69.085us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	91.193us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	331.978us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	228.206us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	132.175us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	91.193us	20	20	100.00
		aes_csr_aliasing	7.000s	228.206us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	373.507us	50	50	100.00
		aes_config_error	9.000s	272.119us	50	50	100.00
		aes_stress	10.000s	2.905ms	50	50	100.00
V2	key_length	aes_smoke	8.000s	373.507us	50	50	100.00
		aes_config_error	9.000s	272.119us	50	50	100.00
		aes_stress	10.000s	2.905ms	50	50	100.00
V2	back2back	aes_stress	10.000s	2.905ms	50	50	100.00
		aes_b2b	24.000s	1.019ms	50	50	100.00
V2	backpressure	aes_stress	10.000s	2.905ms	50	50	100.00
V2	multi_message	aes_smoke	8.000s	373.507us	50	50	100.00
		aes_config_error	9.000s	272.119us	50	50	100.00
		aes_stress	10.000s	2.905ms	50	50	100.00
		aes_alert_reset	11.000s	520.870us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	59.214us	50	50	100.00
		aes_config_error	9.000s	272.119us	50	50	100.00
		aes_alert_reset	11.000s	520.870us	50	50	100.00
V2	trigger_clear_test	aes_clear	19.000s	666.068us	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	50.000s	3.474ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	11.000s	520.870us	50	50	100.00
V2	stress	aes_stress	10.000s	2.905ms	50	50	100.00
V2	sideload	aes_stress	10.000s	2.905ms	50	50	100.00
		aes_sideload	1.017m	3.289ms	50	50	100.00
V2	deinitialization	aes_deinit	32.000s	1.667ms	50	50	100.00
V2	stress_all	aes_stress_all	54.000s	1.153ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	68.899us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	178.599us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	178.599us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	69.085us	5	5	100.00
		aes_csr_rw	5.000s	91.193us	20	20	100.00
		aes_csr_aliasing	7.000s	228.206us	5	5	100.00
		aes_same_csr_outstanding	5.000s	66.885us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	69.085us	5	5	100.00
		aes_csr_rw	5.000s	91.193us	20	20	100.00
		aes_csr_aliasing	7.000s	228.206us	5	5	100.00
		aes_same_csr_outstanding	5.000s	66.885us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	44.000s	4.023ms	50	50	100.00
V2S	fault_inject	aes_fi	13.000s	466.476us	50	50	100.00
		aes_control_fi	36.000s	10.020ms	288	300	96.00
		aes_cipher_fi	43.000s	10.037ms	333	350	95.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	365.907us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	365.907us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	365.907us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	365.907us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	752.405us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	2.070ms	5	5	100.00
		aes_tl_intg_err	6.000s	155.703us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	155.703us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	11.000s	520.870us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	365.907us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	373.507us	50	50	100.00
		aes_stress	10.000s	2.905ms	50	50	100.00
		aes_alert_reset	11.000s	520.870us	50	50	100.00
		aes_core_fi	49.000s	10.005ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	365.907us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	778.181us	50	50	100.00
		aes_stress	10.000s	2.905ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	10.000s	2.905ms	50	50	100.00
		aes_sideload	1.017m	3.289ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	778.181us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	778.181us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	778.181us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	778.181us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	778.181us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	10.000s	2.905ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	10.000s	2.905ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	466.476us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	466.476us	50	50	100.00
		aes_control_fi	36.000s	10.020ms	288	300	96.00
		aes_cipher_fi	43.000s	10.037ms	333	350	95.14
		aes_ctr_fi	9.000s	670.351us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	466.476us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	466.476us	50	50	100.00
		aes_control_fi	36.000s	10.020ms	288	300	96.00
		aes_cipher_fi	43.000s	10.037ms	333	350	95.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	43.000s	10.037ms	333	350	95.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	466.476us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	466.476us	50	50	100.00
		aes_control_fi	36.000s	10.020ms	288	300	96.00
		aes_ctr_fi	9.000s	670.351us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	466.476us	50	50	100.00
		aes_control_fi	36.000s	10.020ms	288	300	96.00
		aes_cipher_fi	43.000s	10.037ms	333	350	95.14
		aes_ctr_fi	9.000s	670.351us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	11.000s	520.870us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	466.476us	50	50	100.00
		aes_control_fi	36.000s	10.020ms	288	300	96.00
		aes_cipher_fi	43.000s	10.037ms	333	350	95.14
		aes_ctr_fi	9.000s	670.351us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	466.476us	50	50	100.00
		aes_control_fi	36.000s	10.020ms	288	300	96.00
		aes_cipher_fi	43.000s	10.037ms	333	350	95.14
		aes_ctr_fi	9.000s	670.351us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	466.476us	50	50	100.00
		aes_control_fi	36.000s	10.020ms	288	300	96.00
		aes_ctr_fi	9.000s	670.351us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	466.476us	50	50	100.00
		aes_control_fi	36.000s	10.020ms	288	300	96.00
		aes_cipher_fi	43.000s	10.037ms	333	350	95.14
V2S		TOTAL			954	985	96.85
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	40.000s	5.245ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1560	1602	97.38

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.38	98.60	96.45	99.44	95.60	97.99	97.78	98.96	97.99

Failure Buckets

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 16 failures:
- Test aes_cipher_fi has 16 failures.
  - 11.aes_cipher_fi.47801484677769939879504093305250487769745157095113516155600385486298043955365
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10054713510 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10054713510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 58.aes_cipher_fi.63487941777954162363685434442934396982139467841713401878963573684301171549141
    Line 146, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/58.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015926746 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015926746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 16.aes_control_fi.63908684375151951062181943879049383932436783512783139553272308738347978224356
    Line 141, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10029379833 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029379833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 57.aes_control_fi.13325219320566974560938795635046808379841549795477666012527055458350203898217
    Line 143, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/57.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10037683021 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10037683021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
Job timed out after * minutes has 6 failures:
- Test aes_control_fi has 5 failures.
  - 25.aes_control_fi.25963456487056369713533702501041587849521228428846285572249571114087278590499
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 96.aes_control_fi.105541444184282675460845567306870687605313779903523648455589321628286664288356
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/96.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 3 more failures.
- Test aes_cipher_fi has 1 failures.
  - 29.aes_cipher_fi.25403172846440393949115196262139597490595144597957205428278507436749515407636
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/29.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

2.aes_stress_all_with_rand_reset.23942759513961776598500726405475540595621750668387858506377737942456213965033
Line 369, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 251107218 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 251107218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.109089391233441595938521345044794468918698291707236812754565906661285702737086
Line 256, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 121161208 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 121161208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 3.aes_stress_all_with_rand_reset.62573931806030326457283932405499518051924762592373174343625945321773410689198
    Line 150, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 380141049 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 380141049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_stress_all_with_rand_reset.39036389988706242764785232757624128036125428209530098750441868710538416946863
    Line 858, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5244899677 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5244899677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

6.aes_core_fi.21783912623959045634930697705790361418646780328051539020835721611552790961728
Line 136, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/6.aes_core_fi/latest/run.log

  UVM_FATAL @ 10004858009 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004858009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aes_core_fi.88397699637775601256408996975707701079507660358449276075791389040448344172811
Line 146, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_core_fi/latest/run.log

  UVM_FATAL @ 10018907073 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018907073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block.status reset value: * has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.106339156882249611486972908516758438167963765695530556521290759936163948564396
    Line 161, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 596780689 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (64 [0x40] vs 0 [0x0]) Regname: aes_reg_block.status reset value: 0x0
  UVM_INFO @ 596780689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.93207917832837844293406005171787370800950146676476259244121874456338828021101
    Line 206, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 406982397 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 406982397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.95947911730542148245469325904813295988489069407406372396136631627751853746290
    Line 437, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 444667402 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 444667402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 26.aes_clear.12814892397247498326943704743739360114537899529530411900739050029458094010524
    Line 4655, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/26.aes_clear/latest/run.log
```
  UVM_FATAL @  59434371 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 1
           TEST FAILED MESSAGES DID NOT MATCH

                 0 9f 	 50 	 43 	 0
                 1 8f 	 7d 	 b7 	 0
```