AES/UNMASKED Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: `c4214fe`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	38.000s	312.173us	1	1	100.00
V1	smoke	aes_smoke	38.000s	70.511us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	61.388us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	109.980us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	497.815us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	214.939us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	388.902us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	109.980us	20	20	100.00
		aes_csr_aliasing	6.000s	214.939us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	38.000s	70.511us	50	50	100.00
		aes_config_error	38.000s	69.037us	50	50	100.00
		aes_stress	38.000s	60.392us	50	50	100.00
V2	key_length	aes_smoke	38.000s	70.511us	50	50	100.00
		aes_config_error	38.000s	69.037us	50	50	100.00
		aes_stress	38.000s	60.392us	50	50	100.00
V2	back2back	aes_stress	38.000s	60.392us	50	50	100.00
		aes_b2b	39.000s	155.195us	50	50	100.00
V2	backpressure	aes_stress	38.000s	60.392us	50	50	100.00
V2	multi_message	aes_smoke	38.000s	70.511us	50	50	100.00
		aes_config_error	38.000s	69.037us	50	50	100.00
		aes_stress	38.000s	60.392us	50	50	100.00
		aes_alert_reset	37.000s	78.928us	50	50	100.00
V2	failure_test	aes_man_cfg_err	37.000s	70.138us	50	50	100.00
		aes_config_error	38.000s	69.037us	50	50	100.00
		aes_alert_reset	37.000s	78.928us	50	50	100.00
V2	trigger_clear_test	aes_clear	39.000s	192.713us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	40.000s	916.753us	1	1	100.00
V2	reset_recovery	aes_alert_reset	37.000s	78.928us	50	50	100.00
V2	stress	aes_stress	38.000s	60.392us	50	50	100.00
V2	sideload	aes_stress	38.000s	60.392us	50	50	100.00
		aes_sideload	33.000s	111.901us	50	50	100.00
V2	deinitialization	aes_deinit	38.000s	78.694us	50	50	100.00
V2	stress_all	aes_stress_all	26.000s	548.482us	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	155.452us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	101.130us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	101.130us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	61.388us	5	5	100.00
		aes_csr_rw	5.000s	109.980us	20	20	100.00
		aes_csr_aliasing	6.000s	214.939us	5	5	100.00
		aes_same_csr_outstanding	5.000s	208.900us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	61.388us	5	5	100.00
		aes_csr_rw	5.000s	109.980us	20	20	100.00
		aes_csr_aliasing	6.000s	214.939us	5	5	100.00
		aes_same_csr_outstanding	5.000s	208.900us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	31.000s	75.604us	50	50	100.00
V2S	fault_inject	aes_fi	29.000s	111.957us	49	50	98.00
		aes_control_fi	39.000s	200.000ms	272	300	90.67
		aes_cipher_fi	36.000s	10.004ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	68.883us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	68.883us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	68.883us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	68.883us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	368.539us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	4.586ms	5	5	100.00
		aes_tl_intg_err	6.000s	145.307us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	145.307us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	37.000s	78.928us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	68.883us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	38.000s	70.511us	50	50	100.00
		aes_stress	38.000s	60.392us	50	50	100.00
		aes_alert_reset	37.000s	78.928us	50	50	100.00
		aes_core_fi	21.000s	10.009ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	68.883us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	37.000s	136.484us	50	50	100.00
		aes_stress	38.000s	60.392us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	38.000s	60.392us	50	50	100.00
		aes_sideload	33.000s	111.901us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	37.000s	136.484us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	37.000s	136.484us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	37.000s	136.484us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	37.000s	136.484us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	37.000s	136.484us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	38.000s	60.392us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	38.000s	60.392us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	29.000s	111.957us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	29.000s	111.957us	49	50	98.00
		aes_control_fi	39.000s	200.000ms	272	300	90.67
		aes_cipher_fi	36.000s	10.004ms	329	350	94.00
		aes_ctr_fi	8.000s	56.303us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	29.000s	111.957us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	29.000s	111.957us	49	50	98.00
		aes_control_fi	39.000s	200.000ms	272	300	90.67
		aes_cipher_fi	36.000s	10.004ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	36.000s	10.004ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	29.000s	111.957us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	29.000s	111.957us	49	50	98.00
		aes_control_fi	39.000s	200.000ms	272	300	90.67
		aes_ctr_fi	8.000s	56.303us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	29.000s	111.957us	49	50	98.00
		aes_control_fi	39.000s	200.000ms	272	300	90.67
		aes_cipher_fi	36.000s	10.004ms	329	350	94.00
		aes_ctr_fi	8.000s	56.303us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	37.000s	78.928us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	29.000s	111.957us	49	50	98.00
		aes_control_fi	39.000s	200.000ms	272	300	90.67
		aes_cipher_fi	36.000s	10.004ms	329	350	94.00
		aes_ctr_fi	8.000s	56.303us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	29.000s	111.957us	49	50	98.00
		aes_control_fi	39.000s	200.000ms	272	300	90.67
		aes_cipher_fi	36.000s	10.004ms	329	350	94.00
		aes_ctr_fi	8.000s	56.303us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	29.000s	111.957us	49	50	98.00
		aes_control_fi	39.000s	200.000ms	272	300	90.67
		aes_ctr_fi	8.000s	56.303us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	29.000s	111.957us	49	50	98.00
		aes_control_fi	39.000s	200.000ms	272	300	90.67
		aes_cipher_fi	36.000s	10.004ms	329	350	94.00
V2S		TOTAL			932	985	94.62
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	22.000s	1.572ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1539	1602	96.07

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.22	97.62	94.67	98.78	93.10	98.07	91.11	98.85	97.99

Failure Buckets

Job timed out after * minutes has 23 failures:
- Test aes_control_fi has 12 failures.
  - 6.aes_control_fi.96034633137689660447664631621280686232945959341066940948829587022013572857389
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 49.aes_control_fi.50692519934965167777754134253288271821340020815534024877283652490794261793094
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 10 failures.
  - 10.aes_cipher_fi.74590912777791973401108777095513384929221140785453012640466947745838123191710
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 15.aes_cipher_fi.110859341419377127538035555713594216709155054807089782592493684484217374696145
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
- Test aes_fi has 1 failures.
  - 25.aes_fi.86559380675224812309284300578108199409506075890914657684318832094685317042468
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/25.aes_fi/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_control_fi has 15 failures.
  - 72.aes_control_fi.49740393788839145114834252393280353357793017874798526016516615588109013966183
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/72.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002795120 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002795120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 78.aes_control_fi.51087561592501081846971316721526485543205586741914584919920179968317595689293
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/78.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10018147726 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018147726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 12.aes_cipher_fi.34499687145387485129947142494659967642583897012630556194846121253610719688100
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/12.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011410657 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011410657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 38.aes_cipher_fi.86046766216342754863440932511377448372745825109894871150365325709232018427616
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/38.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016221865 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016221865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.91862187388931353265369922817179827781399043958659954759344755643863309086075
Line 1082, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 643342434 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 643342434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.27924964859687521858013550608384306863443311612531714902443940060819807615960
Line 173, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  32153800 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  32153800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 25.aes_core_fi.10976217135211011949980828306410825652471067474179349358788734751830416160191
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011364017 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011364017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 51.aes_core_fi.44229731797487978688972639117297766653154975995055819977983790557900126291328
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/51.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009457732 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009457732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.42599617074017227485293037586009121629086602124405014932324577106924324000959
    Line 162, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  74398879 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  74398879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 63.aes_core_fi.32550556131774266784133518258960777849035359982252087232194606137433417688452
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/63.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10026017982 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026017982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 168.aes_control_fi.113871006110968235789375284135743250864551625270125976216446747493650109446078
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/168.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```