CSRNG Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: `c4214fe`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	10.000s	254.821us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	73.413us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	84.403us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	39.000s	3.580ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	11.000s	257.495us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	10.000s	449.782us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	84.403us	20	20	100.00
		csrng_csr_aliasing	11.000s	257.495us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	28.000s	1.291ms	167	200	83.50
V2	alerts	csrng_alert	1.300m	6.154ms	500	500	100.00
V2	err	csrng_err	7.000s	39.511us	455	500	91.00
V2	cmds	csrng_cmds	9.533m	44.896ms	50	50	100.00
V2	life cycle	csrng_cmds	9.533m	44.896ms	50	50	100.00
V2	stress_all	csrng_stress_all	15.383m	23.707ms	49	50	98.00
V2	intr_test	csrng_intr_test	7.000s	177.750us	50	50	100.00
V2	alert_test	csrng_alert_test	11.000s	134.343us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	20.000s	1.431ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	20.000s	1.431ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	73.413us	5	5	100.00
		csrng_csr_rw	6.000s	84.403us	20	20	100.00
		csrng_csr_aliasing	11.000s	257.495us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	158.700us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	73.413us	5	5	100.00
		csrng_csr_rw	6.000s	84.403us	20	20	100.00
		csrng_csr_aliasing	11.000s	257.495us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	158.700us	20	20	100.00
V2		TOTAL			1361	1440	94.51
V2S	tl_intg_err	csrng_sec_cm	15.000s	260.341us	5	5	100.00
		csrng_tl_intg_err	14.000s	917.314us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	21.881us	50	50	100.00
		csrng_csr_rw	6.000s	84.403us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.300m	6.154ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	15.383m	23.707ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
		csrng_sec_cm	15.000s	260.341us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
		csrng_sec_cm	15.000s	260.341us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
		csrng_sec_cm	15.000s	260.341us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
		csrng_sec_cm	15.000s	260.341us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
		csrng_sec_cm	15.000s	260.341us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
		csrng_sec_cm	15.000s	260.341us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
		csrng_sec_cm	15.000s	260.341us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.300m	6.154ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	15.383m	23.707ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.300m	6.154ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	917.314us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
		csrng_sec_cm	15.000s	260.341us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
		csrng_sec_cm	15.000s	260.341us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	28.000s	1.291ms	167	200	83.50
		csrng_err	7.000s	39.511us	455	500	91.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	3.317m	16.502ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1541	1630	94.54

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.56	98.51	96.38	99.83	97.36	92.08	88.00	96.13	89.94

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_cipher_control_fsm.sv,452): Assertion u_state_regs_A has failed has 45 failures:

Test csrng_intr has 18 failures.

41.csrng_intr.35275185355678896207403527795565021524623547807182602792422053826798312376477
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/41.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 51672979 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[2].gen_fsm_n.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @  51672979 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  51672979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.csrng_intr.59039158876468261767691618909128515896332705946712328714247463490504787722960
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/43.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 423674400 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[1].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @ 423674400 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 423674400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 16 more failures.

Test csrng_err has 27 failures.

42.csrng_err.18590282579156890327216831047675485754994630568949188686832691650441001786605
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/42.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 1946494 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[0].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @   1946494 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   1946494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

59.csrng_err.104978956151508060491848782065746605232480124236451046100928133056190996897855
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/59.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 9556497 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[1].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @   9556497 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   9556497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 25 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test csrng_stress_all_with_rand_reset has 10 failures.
  - 0.csrng_stress_all_with_rand_reset.21879686213886995791287663566623666559845569529377471774047569354960175245096
    Line 126, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3461328794 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3461328794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.csrng_stress_all_with_rand_reset.53705225217592177101258031955199097157121057170886902510320181370652289710510
    Line 119, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16501820832 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16501820832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_main_sm.sv,35): Assertion u_state_regs_A has failed has 9 failures:

Test csrng_err has 7 failures.

16.csrng_err.77878761389755216010674985256768615229532706761948579550007550286885067566420
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/16.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 7296393 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @   7296393 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   7296393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.csrng_err.87490758091666478405871173721828276646785333478263023519337529973568422521279
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/24.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 1873772 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @   1873772 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   1873772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test csrng_intr has 2 failures.

35.csrng_intr.12627908100437692573163547723838978002143383163234169568631783506363181131154
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/35.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 459513386 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @ 459513386 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 459513386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

52.csrng_intr.11972842734755766082709140395858419159487469171114616384935924804276325123775
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/52.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 159111580 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @ 159111580 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 159111580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_upd.sv,188): Assertion u_blk_enc_state_regs_A has failed has 8 failures:

Test csrng_intr has 4 failures.

10.csrng_intr.100423685086905537865700643436684688594129165770675097053813311652359545315247
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/10.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 140673075 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @ 140673075 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @ 140673075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

61.csrng_intr.44874110662015779474418677758551077094451934053826672255971133365704958805798
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/61.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 152917918 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @ 152917918 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @ 152917918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test csrng_err has 4 failures.

342.csrng_err.4697872233772363179840205363437667322391402995857108200089342781614355563511
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/342.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 4464835 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @   4464835 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @   4464835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

343.csrng_err.87607671413282215197417769617286341774051646914872540673027704685314320311390
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/343.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 2751409 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @   2751409 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @   2751409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_upd.sv,222): Assertion u_outblk_state_regs_A has failed has 8 failures:

Test csrng_intr has 2 failures.

15.csrng_intr.56934668465247158991080165942587083351675406215906460436826369829646367169732
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/15.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 373071260 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @ 373071260 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @ 373071260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

142.csrng_intr.40003213147455929763249423087446789247434583497597499441552695165467440451802
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/142.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 34777617 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @  34777617 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @  34777617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test csrng_err has 6 failures.

84.csrng_err.46588104851624265167749973282672226018806021624511429076728187118529128945209
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/84.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 9470260 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @   9470260 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @   9470260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

175.csrng_err.75253632410992323337987531975642794136720773933125059138728973955807648460183
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/175.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 1851397 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @   1851397 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @   1851397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_gen.sv,222): Assertion u_state_regs_A has failed has 5 failures:

Test csrng_intr has 4 failures.

19.csrng_intr.104852216349414067574275528433059314787528971369070396608902670310818157298195
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/19.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 107589700 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @ 107589700 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 107589700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

65.csrng_intr.80044276837602729986821486185072788406102410033875730923131893690490374759615
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/65.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 249775252 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @ 249775252 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 249775252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test csrng_err has 1 failures.

61.csrng_err.53273807692952011003989796463424919942359199072227722539780574307485440540121
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/61.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 7735080 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @   7735080 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   7735080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,260): Assertion u_state_regs_A has failed has 3 failures:

Test csrng_intr has 3 failures.

38.csrng_intr.43493249830309865759337013587629397439030303829366549154299753478134496604494
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/38.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,260): (time 265535666 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.u_state_regs_A has failed
  UVM_ERROR @ 265535666 ps: (csrng_cmd_stage.sv:260) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 265535666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

140.csrng_intr.72947386051275875757458285959162502319970414057784941253684682544691898076397
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/140.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,260): (time 122611296 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.u_state_regs_A has failed
  UVM_ERROR @ 122611296 ps: (csrng_cmd_stage.sv:260) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 122611296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 25.csrng_stress_all.24967058748984354393767972778884081092441848305019528753753014965091395634464
    Line 134, in log /nightly/runs/scratch/master/csrng-sim-xcelium/25.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  10731441 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  10731441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```