EDN Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: c4214fe

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.660s 16.696us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.230s 31.250us 5 5 100.00
V1 csr_rw edn_csr_rw 2.430s 18.491us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.790s 263.882us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.750s 43.662us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 3.160s 28.722us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.430s 18.491us 20 20 100.00
edn_csr_aliasing 2.750s 43.662us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.214m 4.474ms 300 300 100.00
V2 csrng_commands edn_genbits 1.214m 4.474ms 300 300 100.00
V2 genbits edn_genbits 1.214m 4.474ms 300 300 100.00
V2 interrupts edn_intr 2.740s 21.930us 50 50 100.00
V2 alerts edn_alert 3.070s 141.743us 200 200 100.00
V2 errs edn_err 2.850s 37.467us 100 100 100.00
V2 disable edn_disable 2.560s 40.600us 50 50 100.00
edn_disable_auto_req_mode 2.910s 35.812us 50 50 100.00
V2 stress_all edn_stress_all 7.480s 388.690us 50 50 100.00
V2 intr_test edn_intr_test 2.380s 32.413us 50 50 100.00
V2 alert_test edn_alert_test 3.010s 86.117us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.840s 406.902us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.840s 406.902us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.230s 31.250us 5 5 100.00
edn_csr_rw 2.430s 18.491us 20 20 100.00
edn_csr_aliasing 2.750s 43.662us 5 5 100.00
edn_same_csr_outstanding 2.510s 97.069us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.230s 31.250us 5 5 100.00
edn_csr_rw 2.430s 18.491us 20 20 100.00
edn_csr_aliasing 2.750s 43.662us 5 5 100.00
edn_same_csr_outstanding 2.510s 97.069us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.410s 877.707us 5 5 100.00
edn_tl_intg_err 6.720s 420.203us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.300s 17.831us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 3.070s 141.743us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.410s 877.707us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.410s 877.707us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.410s 877.707us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.410s 877.707us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 3.070s 141.743us 200 200 100.00
edn_sec_cm 8.410s 877.707us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 3.070s 141.743us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 6.720s 420.203us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.925m 30.936ms 33 50 66.00
V3 TOTAL 33 50 66.00
TOTAL 1113 1130 98.50

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.81 98.87 94.23 97.07 91.28 96.33 99.78 93.13

Failure Buckets