ENTROPY_SRC Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: c4214fe

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 6.000s 83.166us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 40.000s 69.035us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 40.000s 164.834us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 41.000s 535.748us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 40.000s 220.958us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 37.000s 68.971us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 40.000s 164.834us 20 20 100.00
entropy_src_csr_aliasing 40.000s 220.958us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 6.000s 83.166us 50 50 100.00
entropy_src_rng 6.317m 13.098ms 19 300 6.33
entropy_src_fw_ov 8.683m 20.022ms 188 300 62.67
V2 firmware_mode entropy_src_fw_ov 8.683m 20.022ms 188 300 62.67
V2 rng_mode entropy_src_rng 6.317m 13.098ms 19 300 6.33
V2 rng_max_rate entropy_src_rng_max_rate 4.767m 8.441ms 5 400 1.25
V2 health_checks entropy_src_rng 6.317m 13.098ms 19 300 6.33
V2 conditioning entropy_src_rng 6.317m 13.098ms 19 300 6.33
V2 interrupts entropy_src_rng 6.317m 13.098ms 19 300 6.33
entropy_src_intr 22.000s 9.489ms 50 50 100.00
V2 alerts entropy_src_rng 6.317m 13.098ms 19 300 6.33
entropy_src_functional_alerts 7.000s 216.238us 50 50 100.00
V2 stress_all entropy_src_stress_all 6.450m 20.242ms 49 50 98.00
V2 functional_errors entropy_src_functional_errors 7.283m 10.013ms 970 1000 97.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 31.000s 1.336ms 50 50 100.00
V2 intr_test entropy_src_intr_test 40.000s 102.636us 50 50 100.00
V2 alert_test entropy_src_alert_test 6.000s 15.511us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 41.000s 102.763us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 41.000s 102.763us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 40.000s 69.035us 5 5 100.00
entropy_src_csr_rw 40.000s 164.834us 20 20 100.00
entropy_src_csr_aliasing 40.000s 220.958us 5 5 100.00
entropy_src_same_csr_outstanding 37.000s 67.797us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 40.000s 69.035us 5 5 100.00
entropy_src_csr_rw 40.000s 164.834us 20 20 100.00
entropy_src_csr_aliasing 40.000s 220.958us 5 5 100.00
entropy_src_same_csr_outstanding 37.000s 67.797us 20 20 100.00
V2 TOTAL 1521 2340 65.00
V2S tl_intg_err entropy_src_sec_cm 5.000s 169.627us 5 5 100.00
entropy_src_tl_intg_err 41.000s 314.398us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 6.317m 13.098ms 19 300 6.33
entropy_src_cfg_regwen 6.000s 17.435us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 6.317m 13.098ms 19 300 6.33
V2S sec_cm_config_redun entropy_src_rng 6.317m 13.098ms 19 300 6.33
V2S sec_cm_intersig_mubi entropy_src_rng 6.317m 13.098ms 19 300 6.33
entropy_src_fw_ov 8.683m 20.022ms 188 300 62.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 7.283m 10.013ms 970 1000 97.00
entropy_src_sec_cm 5.000s 169.627us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 7.283m 10.013ms 970 1000 97.00
entropy_src_sec_cm 5.000s 169.627us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 6.317m 13.098ms 19 300 6.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 7.283m 10.013ms 970 1000 97.00
entropy_src_sec_cm 5.000s 169.627us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 7.283m 10.013ms 970 1000 97.00
entropy_src_sec_cm 5.000s 169.627us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 7.283m 10.013ms 970 1000 97.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 216.238us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 41.000s 314.398us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.667m 15.024ms 4 50 8.00
V3 TOTAL 4 50 8.00
TOTAL 1705 2570 66.34

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.01 98.17 95.37 98.35 95.41 96.26 96.88 91.01 86.18

Failure Buckets