HMAC Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: c4214fe

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	13.270s	4.485ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.510s	114.243us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.430s	104.155us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	17.490s	1.066ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	10.230s	2.158ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	8.250m	43.792ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.430s	104.155us	20	20	100.00
		hmac_csr_aliasing	10.230s	2.158ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.222m	10.036ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.454m	1.675ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.498m	14.371ms	30	30	100.00
		hmac_test_sha384_vectors	8.639m	28.346ms	75	75	100.00
		hmac_test_sha512_vectors	9.300m	58.913ms	75	75	100.00
		hmac_test_hmac256_vectors	15.610s	616.548us	50	50	100.00
		hmac_test_hmac384_vectors	18.450s	783.458us	60	60	100.00
		hmac_test_hmac512_vectors	21.770s	443.256us	75	75	100.00
V2	burst_wr	hmac_burst_wr	44.380s	3.559ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	19.970m	6.331ms	10	10	100.00
V2	error	hmac_error	1.701m	21.781ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.773m	29.677ms	10	10	100.00
V2	save_and_restore	hmac_smoke	13.270s	4.485ms	10	10	100.00
		hmac_long_msg	1.222m	10.036ms	10	10	100.00
		hmac_back_pressure	1.454m	1.675ms	25	25	100.00
		hmac_datapath_stress	19.970m	6.331ms	10	10	100.00
		hmac_burst_wr	44.380s	3.559ms	50	50	100.00
		hmac_stress_all	41.669m	14.754ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	13.270s	4.485ms	10	10	100.00
		hmac_long_msg	1.222m	10.036ms	10	10	100.00
		hmac_back_pressure	1.454m	1.675ms	25	25	100.00
		hmac_datapath_stress	19.970m	6.331ms	10	10	100.00
		hmac_wipe_secret	1.773m	29.677ms	10	10	100.00
		hmac_test_sha256_vectors	4.498m	14.371ms	30	30	100.00
		hmac_test_sha384_vectors	8.639m	28.346ms	75	75	100.00
		hmac_test_sha512_vectors	9.300m	58.913ms	75	75	100.00
		hmac_test_hmac256_vectors	15.610s	616.548us	50	50	100.00
		hmac_test_hmac384_vectors	18.450s	783.458us	60	60	100.00
		hmac_test_hmac512_vectors	21.770s	443.256us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	13.270s	4.485ms	10	10	100.00
		hmac_long_msg	1.222m	10.036ms	10	10	100.00
		hmac_back_pressure	1.454m	1.675ms	25	25	100.00
		hmac_datapath_stress	19.970m	6.331ms	10	10	100.00
		hmac_burst_wr	44.380s	3.559ms	50	50	100.00
		hmac_error	1.701m	21.781ms	10	10	100.00
		hmac_wipe_secret	1.773m	29.677ms	10	10	100.00
		hmac_test_sha256_vectors	4.498m	14.371ms	30	30	100.00
		hmac_test_sha384_vectors	8.639m	28.346ms	75	75	100.00
		hmac_test_sha512_vectors	9.300m	58.913ms	75	75	100.00
		hmac_test_hmac256_vectors	15.610s	616.548us	50	50	100.00
		hmac_test_hmac384_vectors	18.450s	783.458us	60	60	100.00
		hmac_test_hmac512_vectors	21.770s	443.256us	75	75	100.00
		hmac_stress_all	41.669m	14.754ms	50	50	100.00
V2	stress_all	hmac_stress_all	41.669m	14.754ms	50	50	100.00
V2	alert_test	hmac_alert_test	3.480s	15.049us	50	50	100.00
V2	intr_test	hmac_intr_test	2.190s	19.178us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.860s	209.229us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.860s	209.229us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.510s	114.243us	5	5	100.00
		hmac_csr_rw	2.430s	104.155us	20	20	100.00
		hmac_csr_aliasing	10.230s	2.158ms	5	5	100.00
		hmac_same_csr_outstanding	3.790s	1.243ms	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.510s	114.243us	5	5	100.00
		hmac_csr_rw	2.430s	104.155us	20	20	100.00
		hmac_csr_aliasing	10.230s	2.158ms	5	5	100.00
		hmac_same_csr_outstanding	3.790s	1.243ms	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	3.890s	115.098us	5	5	100.00
		hmac_tl_intg_err	5.890s	484.134us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.890s	484.134us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	13.270s	4.485ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	7.970s	505.246us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	14.451m	211.461ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	3.740s	10.125us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.09	100.00	97.31	100.00	100.00	100.00	100.00	47.30