I2C Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: `c4214fe`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.476m	18.243ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	38.410s	5.692ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.090s	86.750us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.210s	28.145us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.280s	2.090ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.010s	412.855us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.610s	27.173us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.210s	28.145us	20	20	100.00
		i2c_csr_aliasing	3.010s	412.855us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	10.460s	1.033ms	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	53.313m	102.563ms	14	50	28.00
V2	host_maxperf	i2c_host_perf	12.583m	26.676ms	50	50	100.00
V2	host_override	i2c_host_override	2.220s	119.927us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.316m	6.388ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.646m	2.365ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.920s	139.373us	50	50	100.00
		i2c_host_fifo_fmt_empty	28.080s	1.077ms	50	50	100.00
		i2c_host_fifo_reset_rx	15.270s	939.870us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.425m	6.579ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	34.190s	793.720us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	7.770s	171.968us	15	50	30.00
V2	target_glitch	i2c_target_glitch	17.890s	2.198ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	17.016m	41.198ms	49	50	98.00
V2	target_maxperf	i2c_target_perf	10.750s	1.992ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.262m	3.396ms	50	50	100.00
		i2c_target_intr_smoke	11.950s	9.407ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	4.180s	312.264us	50	50	100.00
		i2c_target_fifo_reset_tx	3.300s	439.355us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	19.356m	64.515ms	50	50	100.00
		i2c_target_stress_rd	1.262m	3.396ms	50	50	100.00
		i2c_target_intr_stress_wr	5.311m	25.384ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	11.690s	1.589ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	2.606m	3.668ms	41	50	82.00
V2	bad_address	i2c_target_bad_addr	12.770s	5.731ms	49	50	98.00
V2	target_mode_glitch	i2c_target_hrst	34.120s	10.080ms	24	50	48.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.290s	2.519ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.250s	970.008us	48	50	96.00
V2	host_mode_config_perf	i2c_host_perf	12.583m	26.676ms	50	50	100.00
		i2c_host_perf_precise	35.347m	23.206ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	34.190s	793.720us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	11.610s	818.983us	46	50	92.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.220s	2.161ms	50	50	100.00
		i2c_target_nack_acqfull_addr	5.220s	569.341us	50	50	100.00
		i2c_target_nack_txstretch	3.490s	2.413ms	31	50	62.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	20.910s	1.068ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	5.230s	555.433us	50	50	100.00
V2	alert_test	i2c_alert_test	2.170s	22.521us	50	50	100.00
V2	intr_test	i2c_intr_test	2.230s	19.211us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.940s	104.073us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.940s	104.073us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.090s	86.750us	5	5	100.00
		i2c_csr_rw	2.210s	28.145us	20	20	100.00
		i2c_csr_aliasing	3.010s	412.855us	5	5	100.00
		i2c_same_csr_outstanding	2.550s	55.394us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.090s	86.750us	5	5	100.00
		i2c_csr_rw	2.210s	28.145us	20	20	100.00
		i2c_csr_aliasing	3.010s	412.855us	5	5	100.00
		i2c_same_csr_outstanding	2.550s	55.394us	20	20	100.00
V2		TOTAL			1659	1792	92.58
V2S	tl_intg_err	i2c_tl_intg_err	3.680s	4.135ms	20	20	100.00
		i2c_sec_cm	2.510s	283.719us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.680s	4.135ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	28.460s	1.112ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	4.600s	437.558us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.011m	600.000ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1839	2042	90.06

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.06	97.47	89.59	74.17	72.62	94.18	98.52	89.85

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 47 failures:

Test i2c_host_stress_all has 28 failures.

0.i2c_host_stress_all.58796124860702670357627792913074740683579745993773262364778357296063331970774
Line 284, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 23453507338 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @6467504

1.i2c_host_stress_all.2933997580914865290175540389875159930118908470682253879265305585448920729406
Line 156, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 63263644891 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4317160

... and 26 more failures.

Test i2c_host_mode_toggle has 19 failures.

0.i2c_host_mode_toggle.89101390560403238023638081220262807802508609595038944013650263901929615917168
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 101701875 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @12855

1.i2c_host_mode_toggle.39442697954429707473912784061363275419771449749892835885526750863408990889012
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 129661894 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @116563

... and 17 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
- Test i2c_target_hrst has 26 failures.
  - 0.i2c_target_hrst.82247381523964987628447203880992921106155801821069905422495873070200315670531
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 11783571833 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 11783571833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_hrst.60199976320026998558456746382563834831112690052983960586222587836838353195504
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10057459812 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10057459812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 24 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 22 failures:
- Test i2c_target_unexp_stop has 21 failures.
  - 0.i2c_target_unexp_stop.8875217579396613520033375087806573156713515781431691089241145994835086495742
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  63511867 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 224 [0xe0])
  UVM_INFO @  63511867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_unexp_stop.111910829066599465267903037029677292988603942129508462475458136239854494899815
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 222380231 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 25 [0x19])
  UVM_INFO @ 222380231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 19 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 7.i2c_target_stress_all_with_rand_reset.75322929901026632474946894188318933464519768039897377192523219976451969902569
    Line 128, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7086619274 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 26 [0x1a])
  UVM_INFO @ 7086619274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 20 failures:
- Test i2c_target_unexp_stop has 20 failures.
  - 3.i2c_target_unexp_stop.58259095403334614149963479077539496378464624591904396687364994530228958005975
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 115504414 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 115504414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_unexp_stop.1046525950501442326341881014893117622184341643779100100186334965691968012043
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 249969064 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 249969064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 19 failures:
- Test i2c_target_nack_txstretch has 19 failures.
  - 1.i2c_target_nack_txstretch.64696000446535977739746566927436148227664939538539782188976058330408868919037
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 138682365 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 138682365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_nack_txstretch.47188392641889919441452987346766492161268351316215631630761854841693137327887
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 382907232 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 382907232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.32123866362353498119669857051232260068351264750753196837113605078718809175650
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 374847559 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 374847559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.69588641928095139654153139579316528211877330141474020389612873145423778038002
Line 102, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4933271652 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4933271652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

0.i2c_target_stress_all_with_rand_reset.16314503865631807562666817316421081133707904660601256371740795084162055630261
Line 97, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3862558094 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3862558094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.105574458790453307360970101713689286419112353977038193268233567516860523393707
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4857462989 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4857462989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:

Test i2c_host_mode_toggle has 10 failures.

3.i2c_host_mode_toggle.88589450890388301931544291165242722081787333631043812629939663519551034601159
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 101439217 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

7.i2c_host_mode_toggle.19129072597143452431072016720261537691578695407527019021819259443999450895882
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  72273415 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 8 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 9 failures:
- Test i2c_target_stretch has 9 failures.
  - 4.i2c_target_stretch.81479466033270036339902928554111118374451156135420168488168112766020049200978
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10013515614 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10013515614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_stretch.33434339848252977485242458820549514305965016357541344309233015631985007042421
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10045990350 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10045990350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 9 failures:

Test i2c_target_unexp_stop has 9 failures.

5.i2c_target_unexp_stop.85890060851241864383574648160076445297530108986958617068099931615564791517318
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 328317430 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 328317430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_target_unexp_stop.64041291325258813369019959772803057599221600312707786143117876119097795562572
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 437557758 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 437557758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 6 failures:
- Test i2c_target_tx_stretch_ctrl has 4 failures.
  - 4.i2c_target_tx_stretch_ctrl.104551285994705799780440941924649699477047751420381574915081140288112748448513
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 31.i2c_target_tx_stretch_ctrl.20283323059963646093735666650051197455351331202133332033902910526260048191545
    Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/31.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 2 more failures.
- Test i2c_target_fifo_watermarks_tx has 2 failures.
  - 10.i2c_target_fifo_watermarks_tx.15844676882108820845421202439881416372131957730433664554649648084564252694962
    Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 43.i2c_target_fifo_watermarks_tx.62722099623307232465301849005432883851125743878020799009309009980529782481225
    Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/43.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 5 failures:
- Test i2c_host_mode_toggle has 5 failures.
  - 18.i2c_host_mode_toggle.101837078505085025322605253024281726360566455100478713187894269013014204298438
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 155253557 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xeab25a14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 155253557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 26.i2c_host_mode_toggle.95055748106966728827294213089499120625371375562347417218222180877915253167166
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/26.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 193665679 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xf9af5d94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 193665679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
Job timed out after * minutes has 4 failures:
- Test i2c_host_stress_all has 4 failures.
  - 11.i2c_host_stress_all.35425116758123687423633313829913082110434722803079733526910073542241478718031
    Log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 15.i2c_host_stress_all.55818175772013968542653955169997804000117393601884757305460404544140976157998
    Log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 2.i2c_target_stress_all_with_rand_reset.110144486118455484995916272046799616103606985294379742090085572758134449039145
    Line 141, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_host_stress_all has 1 failures.
  - 39.i2c_host_stress_all.58574609087225660199968024646539660150721575153135527529900106062811762826816
    Line 111, in log /nightly/runs/scratch/master/i2c-sim-vcs/39.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_bad_addr has 1 failures.
  - 43.i2c_target_bad_addr.64740326506971638568061894938747207225324798561628506271141856705388891281083
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/43.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:

Test i2c_host_stress_all has 3 failures.

14.i2c_host_stress_all.47274040389063554251491385632326189219987615699219428637168885335033731674146
Line 166, in log /nightly/runs/scratch/master/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 19098513475 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4265544

38.i2c_host_stress_all.49162069120525279648100707862025454546598037641919833538611203898773784216219
Line 269, in log /nightly/runs/scratch/master/i2c-sim-vcs/38.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 10744694919 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @11148880

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 1.i2c_target_stress_all_with_rand_reset.15852023231040530532381681384657848698092742140837997126598685030427409875988
    Line 114, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3278804592 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3278804592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all has 1 failures.
  - 28.i2c_target_stress_all.80970110736048032619089491084668005687327070320216743264705768970153954644987
    Line 76, in log /nightly/runs/scratch/master/i2c-sim-vcs/28.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 43721707942 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 43721707942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 35.i2c_host_mode_toggle.26383175268141248906089277619440960082170823093306313977709287418513907372326
    Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/35.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```