KEYMGR Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: `c4214fe`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	22.390s	5.164ms	50	50	100.00
V1	random	keymgr_random	56.170s	8.103ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.500s	50.215us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.250s	57.983us	19	20	95.00
V1	csr_bit_bash	keymgr_csr_bit_bash	18.290s	1.789ms	3	5	60.00
V1	csr_aliasing	keymgr_csr_aliasing	10.700s	375.644us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.260s	207.486us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.250s	57.983us	19	20	95.00
		keymgr_csr_aliasing	10.700s	375.644us	4	5	80.00
V1		TOTAL			150	155	96.77
V2	cfgen_during_op	keymgr_cfg_regwen	1.321m	11.641ms	49	50	98.00
V2	sideload	keymgr_sideload	40.300s	5.384ms	49	50	98.00
		keymgr_sideload_kmac	45.910s	1.856ms	50	50	100.00
		keymgr_sideload_aes	40.500s	4.569ms	50	50	100.00
		keymgr_sideload_otbn	28.940s	12.904ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	24.420s	1.392ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	5.430s	229.044us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	8.190s	433.192us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	54.060s	18.046ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	26.730s	1.060ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	14.740s	2.833ms	50	50	100.00
V2	stress_all	keymgr_stress_all	2.391m	9.471ms	49	50	98.00
V2	intr_test	keymgr_intr_test	2.220s	35.109us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.860s	40.026us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.260s	139.996us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.260s	139.996us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.500s	50.215us	5	5	100.00
		keymgr_csr_rw	2.250s	57.983us	19	20	95.00
		keymgr_csr_aliasing	10.700s	375.644us	4	5	80.00
		keymgr_same_csr_outstanding	4.140s	198.859us	12	20	60.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.500s	50.215us	5	5	100.00
		keymgr_csr_rw	2.250s	57.983us	19	20	95.00
		keymgr_csr_aliasing	10.700s	375.644us	4	5	80.00
		keymgr_same_csr_outstanding	4.140s	198.859us	12	20	60.00
V2		TOTAL			729	740	98.51
V2S	sec_cm_additional_check	keymgr_sec_cm	7.710s	699.737us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	7.710s	699.737us	5	5	100.00
		keymgr_tl_intg_err	11.700s	471.283us	17	20	85.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.560s	398.438us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.560s	398.438us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.560s	398.438us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.560s	398.438us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.610s	1.653ms	14	20	70.00
V2S	prim_count_check	keymgr_sec_cm	7.710s	699.737us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	7.710s	699.737us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	11.700s	471.283us	17	20	85.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.560s	398.438us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.321m	11.641ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	56.170s	8.103ms	50	50	100.00
		keymgr_csr_rw	2.250s	57.983us	19	20	95.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	56.170s	8.103ms	50	50	100.00
		keymgr_csr_rw	2.250s	57.983us	19	20	95.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	56.170s	8.103ms	50	50	100.00
		keymgr_csr_rw	2.250s	57.983us	19	20	95.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.430s	229.044us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	26.730s	1.060ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	26.730s	1.060ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	56.170s	8.103ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	17.280s	6.650ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	7.710s	699.737us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	7.710s	699.737us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	7.710s	699.737us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	19.250s	3.890ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.430s	229.044us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	7.710s	699.737us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	7.710s	699.737us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	7.710s	699.737us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	19.250s	3.890ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	19.250s	3.890ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	7.710s	699.737us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	19.250s	3.890ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	7.710s	699.737us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	19.250s	3.890ms	49	50	98.00
V2S		TOTAL			154	165	93.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	21.340s	1.361ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1061	1110	95.59

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.81	99.13	98.07	98.53	100.00	99.10	98.63	91.18

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 22 failures:

Test keymgr_csr_bit_bash has 2 failures.

1.keymgr_csr_bit_bash.82246159351098827594226756546297352083997120153164984303622972046773430850805
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @ 239988902 ps: (keymgr_csr_assert_fpv.sv:400) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @ 239988902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_csr_bit_bash.3701252993095189832304847065951205866317535335661802445715962449536402533029
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @ 2666223625 ps: (keymgr_csr_assert_fpv.sv:460) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @ 2666223625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_shadow_reg_errors_with_csr_rw has 6 failures.

2.keymgr_shadow_reg_errors_with_csr_rw.17733147367394009868342607430622499215268873879856174707053128088465676709109
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @  14405445 ps: (keymgr_csr_assert_fpv.sv:448) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @  14405445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_shadow_reg_errors_with_csr_rw.107662593896070882236722605817350254785563578955653216484263791201704635392987
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
  UVM_ERROR @  28431068 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_1_rd_A
  UVM_INFO @  28431068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_tl_intg_err has 3 failures.

2.keymgr_tl_intg_err.21236562352226188239755392211613951381718224860331732524919912273827473207228
Line 101, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
  UVM_ERROR @  31759792 ps: (keymgr_csr_assert_fpv.sv:454) [ASSERT FAILED] attest_sw_binding_1_rd_A
  UVM_INFO @  31759792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.keymgr_tl_intg_err.42550387360240896188436473577909731078987115781694320633438040015478369623455
Line 85, in log /nightly/runs/scratch/master/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @ 186153652 ps: (keymgr_csr_assert_fpv.sv:430) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @ 186153652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_same_csr_outstanding has 8 failures.

2.keymgr_same_csr_outstanding.7148768847820382215129657414333076207999067321512432701023960649946221485075
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @ 192475447 ps: (keymgr_csr_assert_fpv.sv:442) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @ 192475447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_same_csr_outstanding.73591548635028364230588958330541055428745758501791354934847688145889896001593
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @  23823048 ps: (keymgr_csr_assert_fpv.sv:472) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @  23823048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test keymgr_csr_aliasing has 1 failures.

3.keymgr_csr_aliasing.107405860899826739515157420312360295286766272351223787604626942760287736418383
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @ 868015865 ps: (keymgr_csr_assert_fpv.sv:424) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @ 868015865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test keymgr_stress_all_with_rand_reset has 20 failures.
  - 5.keymgr_stress_all_with_rand_reset.43682417919004609670098460768452422877227012114418690887827989817992316405115
    Line 306, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 428443513 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 428443513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.keymgr_stress_all_with_rand_reset.27290252585394832386390718204379384590526131528385600856532222714963578309032
    Line 102, in log /nightly/runs/scratch/master/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 233069926 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 233069926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.

UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 6 failures:

Test keymgr_stress_all has 1 failures.

0.keymgr_stress_all.55694626528921243853537995709139380484042586083630070776711650055764941739027
Line 1147, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 179628382 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 179628382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_cfg_regwen has 1 failures.

7.keymgr_cfg_regwen.97154126986620800658467671708319947466421079598610640473565719982810824981606
Line 83, in log /nightly/runs/scratch/master/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @   6141553 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   6141553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all_with_rand_reset has 1 failures.

12.keymgr_stress_all_with_rand_reset.23188782702065237027251519972686222466343991885751890137561997734264416400159
Line 1580, in log /nightly/runs/scratch/master/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 210970845 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 210970845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload has 1 failures.

14.keymgr_sideload.54605698093044097972263283893830513120812438280369598835459839645413066850536
Line 90, in log /nightly/runs/scratch/master/keymgr-sim-vcs/14.keymgr_sideload/latest/run.log

  UVM_ERROR @   2237354 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   2237354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload_protect has 1 failures.

22.keymgr_sideload_protect.26031933691342723631460211554712325081938379377333259897057526056554595128647
Line 132, in log /nightly/runs/scratch/master/keymgr-sim-vcs/22.keymgr_sideload_protect/latest/run.log

  UVM_ERROR @  12913975 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  12913975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more tests.

UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation has 1 failures:

Test keymgr_stress_all_with_rand_reset has 1 failures.

1.keymgr_stress_all_with_rand_reset.91942812151767447617410814864719708186758956360186956708176623548612055300868
Line 1201, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 531415651 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (29517670554610439263526438441359380274443784975379919166922554339778962041271272485068204966063336380178591546897161723835376725380140049131069830804285447888156102644399912643306232461825451657789500282885540079932673095317253790751634707223674544970311072321953045088819501704845799283553835594489 [0xb4897c47000000008d4f4a68000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f5073a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9] vs 21393876252302744415100874735577359327392490877768359485674158072710902177430593210695702820048848722766514741784898134972620331763065181050769293762593098155652720110089809259139336101908945944022007297172059417398919978140953674656496681571083776394926776062093906505452406340437778147875519378169 [0x82d999fa0000000000000000000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f5073a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9]) cdi_type: Attestation

   HardwareRevisionSecret act: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9, exp: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9
   RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
   HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e