KMAC/MASKED Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: `c4214fe`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.750m	19.833ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.690s	59.299us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.580s	103.503us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	17.900s	6.903ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.740s	412.836us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.890s	44.200us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.580s	103.503us	20	20	100.00
		kmac_csr_aliasing	10.740s	412.836us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.210s	12.936us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.990s	46.717us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.394m	97.376ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.543m	136.570ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.862m	242.700ms	5	5	100.00
		kmac_test_vectors_sha3_256	34.391m	225.405ms	5	5	100.00
		kmac_test_vectors_sha3_384	25.407m	92.915ms	5	5	100.00
		kmac_test_vectors_sha3_512	15.172m	38.874ms	5	5	100.00
		kmac_test_vectors_shake_128	3.423m	13.829ms	4	5	80.00
		kmac_test_vectors_shake_256	30.849m	87.382ms	5	5	100.00
		kmac_test_vectors_kmac	4.910s	125.361us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.950s	340.592us	5	5	100.00
V2	sideload	kmac_sideload	7.770m	222.527ms	50	50	100.00
V2	app	kmac_app	5.790m	30.609ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.820m	66.677ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.298m	208.161ms	50	50	100.00
V2	error	kmac_error	8.727m	118.448ms	48	50	96.00
V2	key_error	kmac_key_error	22.810s	8.146ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.270s	472.712us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	59.040s	6.972ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	22.970s	2.385ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.538m	7.474ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.050m	1.928ms	50	50	100.00
V2	stress_all	kmac_stress_all	51.224m	496.334ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.320s	47.424us	50	50	100.00
V2	alert_test	kmac_alert_test	2.330s	34.476us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.310s	157.523us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.310s	157.523us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.690s	59.299us	5	5	100.00
		kmac_csr_rw	2.580s	103.503us	20	20	100.00
		kmac_csr_aliasing	10.740s	412.836us	5	5	100.00
		kmac_same_csr_outstanding	4.210s	122.401us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.690s	59.299us	5	5	100.00
		kmac_csr_rw	2.580s	103.503us	20	20	100.00
		kmac_csr_aliasing	10.740s	412.836us	5	5	100.00
		kmac_same_csr_outstanding	4.210s	122.401us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.340s	92.016us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.340s	92.016us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.340s	92.016us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.340s	92.016us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.330s	801.825us	13	20	65.00
V2S	tl_intg_err	kmac_sec_cm	2.027m	7.677ms	5	5	100.00
		kmac_tl_intg_err	6.580s	837.128us	12	20	60.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.580s	837.128us	12	20	60.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.050m	1.928ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.750m	19.833ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.770m	222.527ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.340s	92.016us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.027m	7.677ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.027m	7.677ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.027m	7.677ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.750m	19.833ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.050m	1.928ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.027m	7.677ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.731m	9.148ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.750m	19.833ms	50	50	100.00
V2S		TOTAL			60	75	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	5.004m	7.473ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			919	940	97.77

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.44	99.14	94.47	99.89	80.28	97.09	99.38	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 15 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

1.kmac_shadow_reg_errors_with_csr_rw.73486407441741106588393892722208548420875496597588536027399839021661872592000
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  62917987 ps: (kmac_csr_assert_fpv.sv:524) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  62917987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors_with_csr_rw.3354248617096032054845842516160034629661238571587136055615501055948642041628
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @  64332741 ps: (kmac_csr_assert_fpv.sv:500) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @  64332741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_tl_intg_err has 8 failures.

2.kmac_tl_intg_err.62076386452908163089702140479228572209674873281696945044925124393243332175477
Line 101, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @ 237104696 ps: (kmac_csr_assert_fpv.sv:500) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @ 237104696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_tl_intg_err.55367011755531175393076517059971815543189491651058226458799399526867412148977
Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  30182688 ps: (kmac_csr_assert_fpv.sv:530) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  30182688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 1.kmac_stress_all_with_rand_reset.38156765838705035607648082753230363840929401918085496466475295819652919000643
    Line 179, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2314224815 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2314224815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.kmac_stress_all_with_rand_reset.85518565737755039656716811459182920056660748377652791765769162731675377593430
    Line 130, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3264877468 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 3264877468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test kmac_error has 2 failures.

16.kmac_error.23512648057596814770206907924473288174363017202774463268651440676485270407780
Line 183, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/16.kmac_error/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.kmac_error.18320830788538881656830377876822762954700554094197429655276199776542981250137
Line 266, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/46.kmac_error/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 2.kmac_test_vectors_shake_128.66315568316227195632972128519263016730102039845281499640526191946530489152494
    Line 73, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @  61256014 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  61256014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 2.kmac_stress_all_with_rand_reset.17315853657578027430885883194661111879369517496949405404625772379868515892682
    Line 129, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6857405454 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6857405454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```