KMAC/UNMASKED Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: `c4214fe`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.100m	3.727ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.770s	39.110us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.830s	32.540us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.770s	1.016ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.260s	141.734us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.900s	157.635us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.830s	32.540us	20	20	100.00
		kmac_csr_aliasing	7.260s	141.734us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.630s	13.135us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	3.030s	60.854us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.756m	198.324ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.602m	129.340ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	21.258m	72.051ms	5	5	100.00
		kmac_test_vectors_sha3_256	33.718m	417.311ms	5	5	100.00
		kmac_test_vectors_sha3_384	21.957m	225.499ms	5	5	100.00
		kmac_test_vectors_sha3_512	13.829m	42.228ms	5	5	100.00
		kmac_test_vectors_shake_128	22.854m	20.440ms	5	5	100.00
		kmac_test_vectors_shake_256	22.009m	22.209ms	5	5	100.00
		kmac_test_vectors_kmac	4.190s	119.370us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.750s	33.822us	5	5	100.00
V2	sideload	kmac_sideload	6.293m	102.117ms	50	50	100.00
V2	app	kmac_app	5.611m	54.172ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.634m	54.095ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.066m	35.582ms	50	50	100.00
V2	error	kmac_error	7.965m	67.152ms	50	50	100.00
V2	key_error	kmac_key_error	15.760s	12.632ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.959m	10.057ms	35	50	70.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.490s	7.505ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.680s	5.926ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	53.310s	7.135ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	35.420s	10.306ms	50	50	100.00
V2	stress_all	kmac_stress_all	52.902m	705.662ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.730s	77.474us	50	50	100.00
V2	alert_test	kmac_alert_test	2.380s	27.856us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.620s	634.823us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.620s	634.823us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.770s	39.110us	5	5	100.00
		kmac_csr_rw	2.830s	32.540us	20	20	100.00
		kmac_csr_aliasing	7.260s	141.734us	5	5	100.00
		kmac_same_csr_outstanding	3.750s	125.096us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.770s	39.110us	5	5	100.00
		kmac_csr_rw	2.830s	32.540us	20	20	100.00
		kmac_csr_aliasing	7.260s	141.734us	5	5	100.00
		kmac_same_csr_outstanding	3.750s	125.096us	20	20	100.00
V2		TOTAL			725	740	97.97
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.360s	321.263us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.360s	321.263us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.360s	321.263us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.360s	321.263us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.490s	1.077ms	13	20	65.00
V2S	tl_intg_err	kmac_sec_cm	1.099m	31.443ms	5	5	100.00
		kmac_tl_intg_err	4.920s	143.923us	17	20	85.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.920s	143.923us	17	20	85.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	35.420s	10.306ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.100m	3.727ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.293m	102.117ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.360s	321.263us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.099m	31.443ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.099m	31.443ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.099m	31.443ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.100m	3.727ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	35.420s	10.306ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.099m	31.443ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.329m	54.025ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.100m	3.727ms	50	50	100.00
V2S		TOTAL			65	75	86.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.507m	7.394ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			909	940	96.70

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.85	97.23	94.38	100.00	73.55	95.98	99.35	96.41

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 10 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

0.kmac_shadow_reg_errors_with_csr_rw.80805628001023612383128807064869646519562139722060095431439977970806498424813
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  52161206 ps: (kmac_csr_assert_fpv.sv:536) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  52161206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_shadow_reg_errors_with_csr_rw.13427619365887409710348530224340737490996465188384934388694631103629978093754
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  24979997 ps: (kmac_csr_assert_fpv.sv:494) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  24979997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_tl_intg_err has 3 failures.

12.kmac_tl_intg_err.97399618401535250037614312056199813164566277150794026536621214140959299701169
Line 90, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/12.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  53565102 ps: (kmac_csr_assert_fpv.sv:494) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  53565102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.kmac_tl_intg_err.22821401726618034712553229644159802534933290341284453524356623709237230990838
Line 87, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/14.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  44846668 ps: (kmac_csr_assert_fpv.sv:524) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  44846668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.39364349759240877187433229136083722836197587844156501540004898289121901634353
    Line 108, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 276037087 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 276037087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.kmac_stress_all_with_rand_reset.108510272160688151681276258350231953795387124030144129170130009058099780604115
    Line 201, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12199226718 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 12199226718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 4 failures:
- Test kmac_sideload_invalid has 4 failures.
  - 3.kmac_sideload_invalid.96906095149373422331699781350095440059758726675630192292308865310038235465089
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10010030500 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc5c0000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10010030500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 17.kmac_sideload_invalid.19492441258262421164948697213457979151786724589486642839562168072953884348917
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/17.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10009091201 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfd27000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10009091201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 3 failures:
- Test kmac_sideload_invalid has 3 failures.
  - 18.kmac_sideload_invalid.59181625463815898139148553390983844392730735639251260763632997688161110370460
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10136643110 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x31426000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10136643110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 38.kmac_sideload_invalid.78487220254280468339450942206063680785323315200650274014681184759774170399133
    Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/38.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10338803986 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc7cac000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10338803986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:

Test kmac_sideload_invalid has 2 failures.

2.kmac_sideload_invalid.64578384559779697708084547186222132947271247172157459495055165495949368621580
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log

  UVM_FATAL @ 10103889482 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb9252000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10103889482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.kmac_sideload_invalid.31782529863152671920516467297434465017672924208124706752610332464765099318094
Line 84, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log

  UVM_FATAL @ 10293100215 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb8816000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10293100215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:

Test kmac_sideload_invalid has 2 failures.

12.kmac_sideload_invalid.4546593576720349632883169485173337306510197609363636338802689844186096200218
Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/12.kmac_sideload_invalid/latest/run.log

  UVM_FATAL @ 10056539972 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x25427000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10056539972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.kmac_sideload_invalid.22202720913200383475496707360829428612936378233002802102171500922670498425959
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/22.kmac_sideload_invalid/latest/run.log

  UVM_FATAL @ 10394411613 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x13daf000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10394411613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 9.kmac_stress_all_with_rand_reset.60734029807899154069556616583019144212808592855347965943599904584245639848583
    Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1922166818 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1922166818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 20.kmac_sideload_invalid.106113550178738659874443330862364179714123428056985706606849729778581169287199
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/20.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10149657744 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x626d2000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
  UVM_INFO @ 10149657744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 25.kmac_sideload_invalid.21697960907652867398968626601497924392231793162883269414991610030164699952434
    Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/25.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10384898698 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8c113000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
  UVM_INFO @ 10384898698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 33.kmac_sideload_invalid.63343431137156889654788106333030616085001380812051954019267394805576095906078
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/33.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10103121556 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2f75f000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10103121556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 43.kmac_sideload_invalid.26357710909153789544057386046772642850947228732631664990842199653687598792402
    Line 84, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/43.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10132999424 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3bedb000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
  UVM_INFO @ 10132999424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```