c4214fe| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 11.000s | 153.148us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 43.000s | 138.522us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 16.000s | 63.807us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 10.000s | 15.490us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 14.000s | 144.935us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 10.000s | 45.843us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 12.000s | 115.567us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 10.000s | 15.490us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 10.000s | 45.843us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 33.000s | 1.805ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 20.000s | 440.572us | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 44.000s | 173.330us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 43.000s | 561.551us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 1.800m | 272.489us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.217m | 268.325us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 34.000s | 125.655us | 60 | 60 | 100.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 10.000s | 19.145us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 24.000s | 87.177us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 11.000s | 30.837us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 11.000s | 37.536us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 13.000s | 109.266us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 13.000s | 109.266us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 16.000s | 63.807us | 5 | 5 | 100.00 |
| otbn_csr_rw | 10.000s | 15.490us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 10.000s | 45.843us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 10.000s | 44.995us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 16.000s | 63.807us | 5 | 5 | 100.00 |
| otbn_csr_rw | 10.000s | 15.490us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 10.000s | 45.843us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 10.000s | 44.995us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 246 | 246 | 100.00 | |||
| V2S | mem_integrity | otbn_imem_err | 11.000s | 20.299us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 38.077us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 28.886s | 4 | 5 | 80.00 | |
| otbn_controller_ispr_rdata_err | 11.000s | 221.963us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 28.574s | 3 | 5 | 60.00 | |||
| otbn_urnd_err | 8.000s | 11.655us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 10.000s | 285.578us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 9.000s | 36.883us | 2 | 2 | 100.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 17.000s | 73.751us | 10 | 10 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 |
| otbn_tl_intg_err | 44.000s | 191.270us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 33.000s | 149.486us | 17 | 20 | 85.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 |
| V2S | prim_count_check | otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 11.000s | 153.148us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 16.000s | 38.077us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 11.000s | 20.299us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 44.000s | 191.270us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 34.000s | 125.655us | 60 | 60 | 100.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 11.000s | 20.299us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 38.077us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 10.000s | 19.145us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 10.000s | 285.578us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 43.000s | 138.522us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 20.299us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 38.077us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 10.000s | 19.145us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 10.000s | 285.578us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 34.000s | 125.655us | 60 | 60 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 20.299us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 38.077us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 10.000s | 19.145us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 10.000s | 285.578us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 43.000s | 138.522us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 18.000s | 54.390us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 27.603s | 4 | 5 | 80.00 | |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.000m | 216.315us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.000m | 216.315us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 14.000s | 40.137us | 9 | 10 | 90.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 17.000s | 97.942us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 27.024s | 3 | 5 | 60.00 | |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 27.024s | 3 | 5 | 60.00 | |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 48.000s | 187.301us | 3 | 7 | 42.86 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 43.000s | 138.522us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 43.000s | 138.522us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 43.000s | 138.522us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.800m | 272.489us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 43.000s | 138.522us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 43.000s | 138.522us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 13.000s | 141.332us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 43.000s | 138.522us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 2.300m | 2.115ms | 2 | 5 | 40.00 |
| V2S | TOTAL | 146 | 163 | 89.57 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 9.367m | 2.887ms | 2 | 10 | 20.00 |
| V3 | TOTAL | 2 | 10 | 20.00 | |||
| TOTAL | 560 | 585 | 95.73 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 99.08 | 99.64 | 95.91 | 99.72 | 93.22 | 93.21 | 100.00 | 97.85 | 100.00 |
Job returned non-zero exit code has 6 failures:
Test otbn_alu_bignum_mod_err has 1 failures.
0.otbn_alu_bignum_mod_err.78460725186912452601187379842714713169257409420350582002252444585531384869634
Log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest/run.log
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 78460725186912452601187379842714713169257409420350582002252444585531384869634 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest
2025/06/15 13:00:05 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
[FATAL 13:00:33.712 src/main/cpp/archive_utils.cc:58] Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
./bazelisk.sh: line 198: /nightly/runs/opentitan/.bin/bazelisk: Permission denied
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 126
Test otbn_mac_bignum_acc_err has 2 failures.
0.otbn_mac_bignum_acc_err.109403185961314500854600532614657840805692487696184655920767638309054114345496
Log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest/run.log
make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 109403185961314500854600532614657840805692487696184655920767638309054114345496 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest run_opts='+en_cov=1 -covmodeldir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_mac_bignum_acc_err.771928600 -covworkdir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_mac_bignum_acc_err.771928600 -covoverwrite +otbn_elf_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=771928600 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_mac_bignum_acc_err_vseq -nowarn DSEM2009' seed=109403185961314500854600532614657840805692487696184655920767638309054114345496 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_mac_bignum_acc_err_vseq
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 109403185961314500854600532614657840805692487696184655920767638309054114345496 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest
2025/06/15 13:00:05 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
1.otbn_mac_bignum_acc_err.51011192002448699677514892882865422519522884666500441309929243366957696535903
Log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_mac_bignum_acc_err/latest/run.log
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_mac_bignum_acc_err/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_mac_bignum_acc_err/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 51011192002448699677514892882865422519522884666500441309929243366957696535903 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_mac_bignum_acc_err/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/1.otbn_mac_bignum_acc_err/latest
2025/06/15 13:00:10 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
[FATAL 13:00:33.104 src/main/cpp/archive_utils.cc:58] Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
./bazelisk.sh: line 198: /nightly/runs/opentitan/.bin/bazelisk: Permission denied
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 126
Test otbn_pc_ctrl_flow_redun has 1 failures.
0.otbn_pc_ctrl_flow_redun.26756637802764731137790680348142756864836966506753055042004175725676609897408
Log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest/run.log
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 26756637802764731137790680348142756864836966506753055042004175725676609897408 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest
2025/06/15 13:00:06 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
[FATAL 13:00:33.504 src/main/cpp/archive_utils.cc:58] Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
./bazelisk.sh: line 198: /nightly/runs/opentitan/.bin/bazelisk: Permission denied
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 126
Test otbn_stack_addr_integ_chk has 2 failures.
0.otbn_stack_addr_integ_chk.111810144142023532552288512298419122905068233542584035502774783080375787973941
Log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 111810144142023532552288512298419122905068233542584035502774783080375787973941 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest
2025/06/15 13:00:06 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
[FATAL 13:00:33.497 src/main/cpp/archive_utils.cc:58] Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
./bazelisk.sh: line 198: /nightly/runs/opentitan/.bin/bazelisk: Permission denied
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 126
1.otbn_stack_addr_integ_chk.48664364934687026693468650338760920353934929273474601047364920449871204916455
Log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 48664364934687026693468650338760920353934929273474601047364920449871204916455 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest run_opts='+en_cov=1 -covmodeldir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage/default/1.otbn_stack_addr_integ_chk.2705923303 -covworkdir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 1.otbn_stack_addr_integ_chk.2705923303 -covoverwrite +otbn_elf_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=2705923303 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_stack_addr_integ_chk_vseq -nowarn DSEM2009' seed=48664364934687026693468650338760920353934929273474601047364920449871204916455 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_stack_addr_integ_chk_vseq
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 48664364934687026693468650338760920353934929273474601047364920449871204916455 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
[FATAL 13:00:33.646 src/main/cpp/archive_utils.cc:58] Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
./bazelisk.sh: line 198: /nightly/runs/opentitan/.bin/bazelisk: Permission denied
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 126
UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
0.otbn_stress_all_with_rand_reset.81056874011779443497212550226563513866960997342400208799764891822463353858003
Line 207, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 303184071 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 303184071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.otbn_stress_all_with_rand_reset.82635383265179906430508253350608953447058759803584258313104632231952365042893
Line 186, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 119958974 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 119958974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:
0.otbn_sec_wipe_err.31062216849349026172122252747212937959526429863386070609369019904901660715365
Line 124, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22428643 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 22428643 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 22428643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.otbn_sec_wipe_err.3699766694297028465730737254485362626575921968570635393617773694663553827989
Line 129, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 187301328 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 187301328 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 187301328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 3 failures:
0.otbn_sec_cm.106021526759391474115959479524411986696350379230030425576468766126071309468697
Line 83, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 4252421 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 4252421 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_ERROR @ 4252421 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
UVM_INFO @ 4252421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_sec_cm.96555730914219448538919587482878448013350700674083508133647261831875676419864
Line 120, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 236649302 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 236649302 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_ERROR @ 236649302 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
UVM_INFO @ 236649302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 3 failures:
4.otbn_stress_all_with_rand_reset.109713154799804472316302209111641796329377110710184827273410932422482071428424
Line 240, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 642022351 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 642022351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.otbn_stress_all_with_rand_reset.27031615564448132044810447547267999319591200497552819849838542505035808483159
Line 216, in log /nightly/runs/scratch/master/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 753296744 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 753296744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
8.otbn_passthru_mem_tl_intg_err.59908729726220451946050004018020105792609882832297572275277439105690916344734
Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/8.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 17827455 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 17827455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.otbn_passthru_mem_tl_intg_err.80536846898104581584913653925755793595553502717513733678609742460157785441921
Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/19.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 15649489 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 15649489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:129) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
6.otbn_rf_base_intg_err.765671205224640157064216618405171172865571832011943420428698549555974630809
Line 106, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 40137298 ps: (otbn_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
UVM_INFO @ 40137298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:701) virtual_sequencer [otbn_dmem_err_vseq] expect alert:fatal to fire has 1 failures:
8.otbn_stress_all_with_rand_reset.23491882906599591422080074883920806197929143532005426191970430577849207885001
Line 178, in log /nightly/runs/scratch/master/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 166130880 ps: (cip_base_vseq.sv:701) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] expect alert:fatal to fire
UVM_INFO @ 166130880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:
13.otbn_passthru_mem_tl_intg_err.49878149624298407854297922230398229549378704155248088749979132449847928053130
Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/13.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 34012083 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 34012083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---