c4214fe| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 7.000s | 93.156us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 5.000s | 14.430us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 5.000s | 15.430us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 8.000s | 253.075us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 5.000s | 29.588us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 5.000s | 99.541us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 5.000s | 15.430us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 5.000s | 29.588us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 51.267m | 600.000ms | 27 | 50 | 54.00 |
| V2 | cnt_rollover | cnt_rollover | 1.383m | 10.968ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 5.000s | 19.113us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.988h | 1.407s | 17 | 50 | 34.00 |
| V2 | alert_test | pattgen_alert_test | 5.000s | 16.196us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 5.000s | 13.989us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 6.000s | 225.029us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 6.000s | 225.029us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 5.000s | 14.430us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 15.430us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 29.588us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 123.415us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 5.000s | 14.430us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 15.430us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 29.588us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 123.415us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 284 | 340 | 83.53 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 6.000s | 275.125us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 4.000s | 128.626us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 6.000s | 275.125us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.417m | 8.114ms | 3 | 50 | 6.00 |
| V3 | TOTAL | 3 | 50 | 6.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.467m | 10.003ms | 34 | 50 | 68.00 | |
| TOTAL | 451 | 570 | 79.12 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.80 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 100.00 | 89.42 |
UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 47 failures:
0.pattgen_stress_all_with_rand_reset.110756444363822993555368284785251284772893930908377814926893136016838250705253
Line 175, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 792312749 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 792317984 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 792317984 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 792358388 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.51988325940172655488632470909733497024997711456555711571297271562365956752996
Line 119, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1787405463 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1787408842 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1787408842 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1787513007 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 45 more failures.
Job timed out after * minutes has 29 failures:
2.pattgen_perf.39385343060076012727496411274798782245738028791037495486081121603937027247643
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log
Job timed out after 60 minutes
8.pattgen_perf.84764803207328086353942678154806493673194776224970752764465938876689376832547
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/8.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 15 more failures.
6.pattgen_stress_all.71657791725063426475221539013164164570763554488354978100482860236236229062427
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/6.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
11.pattgen_stress_all.108267157178558909274108091604511473186742954178044374255057163129847698013120
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/11.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 10 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 20 failures:
1.pattgen_stress_all.94566781595014123764245560472559463720100131230597920281154081847526379979584
Line 145, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log
UVM_ERROR @ 970676882 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10403
3.pattgen_stress_all.19557291644693635402058432541023522358002362292811976529874849043483773725375
Line 147, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log
UVM_ERROR @ 23730401189 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @26507
... and 18 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 7 failures:
9.pattgen_perf.7833156892957809150864556213844407628659090114898067850887086392593412528271
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/9.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.pattgen_perf.64080213063884653343613805616630799606960023470192081008102388379636544696026
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/13.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
37.pattgen_stress_all.18400591816449994133611161569499750473578197484079109771586080561925096259432
Line 126, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/37.pattgen_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
5.pattgen_inactive_level.16616864310850676648040657295750815471258321615898362340453633544551634829325
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10006419045 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x62ba9590, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10006419045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.pattgen_inactive_level.90542386599617981400213038483998729161788954467933232393688761945958997335296
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10074907291 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2747d690, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10074907291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 2 failures:
15.pattgen_inactive_level.83986756096081624284885676308196960194430505992180289814673570435553132210586
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10012274533 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xae6f4750, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10012274533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.pattgen_inactive_level.10945524447216884054548886541721339935918543708751809069895331595291783614006
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10010045225 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5800a250, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10010045225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 2 failures:
18.pattgen_inactive_level.62356973816034252910769985158781654486548490244756747309645449761148328803576
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002812121 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc1d4a2d0, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10002812121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.pattgen_inactive_level.79383325276008208367518450857075347573020720328433602121989524675314832103959
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/29.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10004977138 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xdc63f990, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10004977138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 2 failures:
30.pattgen_inactive_level.18196806847770903940605805202199360481201929794483589586016878435784074995790
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10104316958 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x649d4d50, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10104316958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.pattgen_inactive_level.62400124208333785712526086145301936060437616734059919323297552940080415413699
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/43.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10082590955 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x57600790, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10082590955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
10.pattgen_inactive_level.77754297820601038578209951731677240758793991789790546982838594752410103623154
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10026971050 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xead12ad0, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10026971050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
11.pattgen_inactive_level.57873099579348720114409742764155696216021217604487680056976384522571451708485
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10040027047 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2a05edd0, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10040027047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
13.pattgen_inactive_level.74208973131067758656128200157339750286748629459241744187842468569597141717497
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10007712333 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x39756950, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10007712333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
20.pattgen_inactive_level.70554639167017571204463419120559698635353886351947945298921713152827322473150
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/20.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10174186370 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe15e590, Comparison=CompareOpEq, exp_data=0x0, call_count=27)
UVM_INFO @ 10174186370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
23.pattgen_inactive_level.76192672859752277567641987036530602168741579192985455232381575087375479734500
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/23.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10010650287 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x15f24b50, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10010650287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
42.pattgen_inactive_level.83857571851030779916538302611066953371066621224019980744330421068091750998626
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/42.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10022924001 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2c72d290, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 10022924001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
45.pattgen_inactive_level.34143928352300045583144839366066240588651256282109965327125615239966215988564
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10067807965 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x32cb50d0, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10067807965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
49.pattgen_inactive_level.102954703002745154691207042195480371148599034315694063003644773046909589573077
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10012101047 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x3afa3310, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
UVM_INFO @ 10012101047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---