ROM_CTRL/32KB Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: c4214fe

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.110s	177.537us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.580s	179.646us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.430s	166.540us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	8.040s	167.841us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.520s	557.660us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.430s	178.309us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.430s	166.540us	20	20	100.00
		rom_ctrl_csr_aliasing	6.520s	557.660us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.410s	127.786us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.540s	171.123us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.350s	810.030us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	28.040s	602.549us	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	9.470s	1.040ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.270s	164.563us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.990s	577.704us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.990s	577.704us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.580s	179.646us	5	5	100.00
		rom_ctrl_csr_rw	7.430s	166.540us	20	20	100.00
		rom_ctrl_csr_aliasing	6.520s	557.660us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.380s	188.845us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.580s	179.646us	5	5	100.00
		rom_ctrl_csr_rw	7.430s	166.540us	20	20	100.00
		rom_ctrl_csr_aliasing	6.520s	557.660us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.380s	188.845us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.901m	10.299ms	18	20	90.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	33.010s	3.164ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.531m	1.822ms	5	5	100.00
		rom_ctrl_tl_intg_err	59.520s	432.706us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.531m	1.822ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.531m	1.822ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.901m	10.299ms	18	20	90.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.901m	10.299ms	18	20	90.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.901m	10.299ms	18	20	90.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.901m	10.299ms	18	20	90.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.901m	10.299ms	18	20	90.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.531m	1.822ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.531m	1.822ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.110s	177.537us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.110s	177.537us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.110s	177.537us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	59.520s	432.706us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.901m	10.299ms	18	20	90.00
		rom_ctrl_kmac_err_chk	9.470s	1.040ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.901m	10.299ms	18	20	90.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.901m	10.299ms	18	20	90.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.901m	10.299ms	18	20	90.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	33.010s	3.164ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.531m	1.822ms	5	5	100.00
V2S		TOTAL			63	65	96.92
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.777m	56.049ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			264	266	99.25

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.73	99.41	100.00	100.00	100.00	98.98	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 2 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.

    • 1.rom_ctrl_corrupt_sig_fatal_chk.44638287882680476319284725767812046770896247211580733655384520806111308121536
      Line 93, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 812723272 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 812723272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.rom_ctrl_corrupt_sig_fatal_chk.47900916024745919154609365666882093973516985784660529434116848844749327809043
      Line 75, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 520490218 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 520490218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---