RV_TIMER Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: c4214fe

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.840s	50.312us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.760s	54.068us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	1.930s	30.677us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.270s	368.117us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.010s	31.580us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.360s	97.557us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.930s	30.677us	20	20	100.00
		rv_timer_csr_aliasing	2.010s	31.580us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	8.380s	23.996ms	20	20	100.00
V2	disabled	rv_timer_disabled	5.770s	2.872ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	8.444m	534.596ms	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	8.444m	534.596ms	10	10	100.00
V2	stress	rv_timer_stress_all	6.880s	4.551ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.110s	23.593us	50	50	100.00
V2	intr_test	rv_timer_intr_test	1.960s	19.235us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.600s	460.889us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.600s	460.889us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.760s	54.068us	5	5	100.00
		rv_timer_csr_rw	1.930s	30.677us	20	20	100.00
		rv_timer_csr_aliasing	2.010s	31.580us	5	5	100.00
		rv_timer_same_csr_outstanding	2.200s	19.387us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.760s	54.068us	5	5	100.00
		rv_timer_csr_rw	1.930s	30.677us	20	20	100.00
		rv_timer_csr_aliasing	2.010s	31.580us	5	5	100.00
		rv_timer_same_csr_outstanding	2.200s	19.387us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.150s	94.173us	5	5	100.00
		rv_timer_tl_intg_err	2.490s	129.769us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.490s	129.769us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	1.800s	39.942us	10	10	100.00
V3	max_value	rv_timer_max	1.790s	37.681us	10	10	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	51.890s	26.778ms	20	20	100.00
V3		TOTAL			40	40	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.44	100.00	100.00	78.66	--	100.00	100.00	100.00