SPI_DEVICE/1R1W Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: `c4214fe`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.153m	276.775ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	3.050s	296.042us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.750s	544.473us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.660s	2.815ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.990s	1.273ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.950s	62.383us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.750s	544.473us	20	20	100.00
		spi_device_csr_aliasing	22.990s	1.273ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.240s	20.719us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.010s	166.722us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.420s	30.194us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.400s	11.363us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	2.220s	3.485us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	5.660s	81.487us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.660s	81.487us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	30.480s	10.486ms	50	50	100.00
		spi_device_tpm_sts_read	2.680s	224.185us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.480s	40.676ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	40.650s	37.454ms	50	50	100.00
		spi_device_flash_all	6.098m	1.334s	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	39.190s	41.302ms	50	50	100.00
		spi_device_flash_all	6.098m	1.334s	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	39.190s	41.302ms	50	50	100.00
		spi_device_flash_all	6.098m	1.334s	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.098m	1.334s	50	50	100.00
V2	cmd_read_status	spi_device_intercept	24.780s	9.555ms	50	50	100.00
		spi_device_flash_all	6.098m	1.334s	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	24.780s	9.555ms	50	50	100.00
		spi_device_flash_all	6.098m	1.334s	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	24.780s	9.555ms	50	50	100.00
		spi_device_flash_all	6.098m	1.334s	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	24.780s	9.555ms	50	50	100.00
		spi_device_flash_all	6.098m	1.334s	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	24.780s	9.555ms	50	50	100.00
		spi_device_flash_all	6.098m	1.334s	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	49.680s	12.261ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.704m	15.587ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.704m	15.587ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.704m	15.587ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	57.160s	14.402ms	50	50	100.00
		spi_device_read_buffer_direct	20.030s	3.490ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.704m	15.587ms	50	50	100.00
		spi_device_flash_all	6.098m	1.334s	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.098m	1.334s	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.098m	1.334s	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	29.340s	3.385ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	29.340s	3.385ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.153m	276.775ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.783m	293.687ms	50	50	100.00
V2	stress_all	spi_device_stress_all	10.821m	95.281ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.480s	16.232us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.420s	12.725us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.840s	186.757us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.840s	186.757us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	3.050s	296.042us	5	5	100.00
		spi_device_csr_rw	3.750s	544.473us	20	20	100.00
		spi_device_csr_aliasing	22.990s	1.273ms	5	5	100.00
		spi_device_same_csr_outstanding	5.600s	120.055us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	3.050s	296.042us	5	5	100.00
		spi_device_csr_rw	3.750s	544.473us	20	20	100.00
		spi_device_csr_aliasing	22.990s	1.273ms	5	5	100.00
		spi_device_same_csr_outstanding	5.600s	120.055us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.870s	174.646us	5	5	100.00
		spi_device_tl_intg_err	20.830s	1.729ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.830s	1.729ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.163m	99.262ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.80	99.11	96.50	71.19	89.36	98.39	95.76	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.78563042052453924474017609908637827774173816839603687754960978238535493266320
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    892922 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[43])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    892922 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    892922 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[939])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.52219643955697898189385197639890165325940078089337373413020805098884087072730
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   9363157 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[80])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   9363157 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   9363157 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[976])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])

has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.96005254103577028574834444425266698585948341937867166044356440288563124472457
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @    959825 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1279d6 [100100111100111010110] vs 0x0 [0])
  UVM_ERROR @   1024825 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3779f1 [1101110111100111110001] vs 0x0 [0])
  UVM_ERROR @   1080825 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3572d8 [1101010111001011011000] vs 0x0 [0])
  UVM_ERROR @   1101825 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x89b71c [100010011011011100011100] vs 0x0 [0])
  UVM_ERROR @   1121825 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3d89d4 [1111011000100111010100] vs 0x0 [0])