SPI_DEVICE/2P Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: c4214fe

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.201m	87.572ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	3.050s	92.482us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.970s	123.560us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.940s	2.419ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.630s	3.733ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.400s	111.611us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.970s	123.560us	20	20	100.00
		spi_device_csr_aliasing	17.630s	3.733ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.310s	11.405us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.220s	53.245us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.510s	40.010us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.800s	61.469us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.810s	21.328us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.150s	1.091ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.150s	1.091ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.240s	13.017ms	50	50	100.00
		spi_device_tpm_sts_read	2.680s	90.931us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	36.430s	6.117ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	38.660s	46.116ms	50	50	100.00
		spi_device_flash_all	6.448m	128.465ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	30.580s	96.219ms	50	50	100.00
		spi_device_flash_all	6.448m	128.465ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	30.580s	96.219ms	50	50	100.00
		spi_device_flash_all	6.448m	128.465ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.448m	128.465ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	39.170s	15.171ms	50	50	100.00
		spi_device_flash_all	6.448m	128.465ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	39.170s	15.171ms	50	50	100.00
		spi_device_flash_all	6.448m	128.465ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	39.170s	15.171ms	50	50	100.00
		spi_device_flash_all	6.448m	128.465ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	39.170s	15.171ms	50	50	100.00
		spi_device_flash_all	6.448m	128.465ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	39.170s	15.171ms	50	50	100.00
		spi_device_flash_all	6.448m	128.465ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	44.320s	230.684ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.345m	95.494ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.345m	95.494ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.345m	95.494ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.093m	7.741ms	50	50	100.00
		spi_device_read_buffer_direct	15.320s	5.426ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.345m	95.494ms	50	50	100.00
		spi_device_flash_all	6.448m	128.465ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.448m	128.465ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.448m	128.465ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.920s	2.539ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.920s	2.539ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.201m	87.572ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.679m	82.995ms	50	50	100.00
V2	stress_all	spi_device_stress_all	8.673m	76.443ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.440s	13.421us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.370s	151.784us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.300s	535.905us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.300s	535.905us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	3.050s	92.482us	5	5	100.00
		spi_device_csr_rw	3.970s	123.560us	20	20	100.00
		spi_device_csr_aliasing	17.630s	3.733ms	5	5	100.00
		spi_device_same_csr_outstanding	5.630s	753.467us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	3.050s	92.482us	5	5	100.00
		spi_device_csr_rw	3.970s	123.560us	20	20	100.00
		spi_device_csr_aliasing	17.630s	3.733ms	5	5	100.00
		spi_device_same_csr_outstanding	5.630s	753.467us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.480s	92.310us	5	5	100.00
		spi_device_tl_intg_err	18.800s	9.118ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.800s	9.118ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	3.270m	135.427ms	50	50	100.00
		TOTAL			1151	1151	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.33	99.17	96.60	74.78	89.36	98.47	95.74	99.21