SPI_HOST Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: `c4214fe`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.017m	21.059ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	122.326us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	16.463us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	236.626us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	26.738us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	46.284us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	16.463us	20	20	100.00
		spi_host_csr_aliasing	4.000s	26.738us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	17.464us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	139.521us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	39.000s	22.774us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	1.450m	4.099ms	50	50	100.00
		spi_host_error_cmd	39.000s	37.427us	50	50	100.00
		spi_host_event	13.067m	42.468ms	50	50	100.00
V2	clock_rate	spi_host_speed	1.833m	200.000ms	49	50	98.00
V2	speed	spi_host_speed	1.833m	200.000ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	1.833m	200.000ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	3.783m	14.415ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	39.000s	24.707us	50	50	100.00
V2	cpol_cpha	spi_host_speed	1.833m	200.000ms	49	50	98.00
V2	full_cycle	spi_host_speed	1.833m	200.000ms	49	50	98.00
V2	duplex	spi_host_smoke	2.017m	21.059ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.017m	21.059ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.150m	1.638ms	50	50	100.00
V2	spien	spi_host_spien	4.350m	7.336ms	50	50	100.00
V2	stall	spi_host_status_stall	11.017m	16.545ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	41.000s	1.909ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	1.450m	4.099ms	50	50	100.00
V2	alert_test	spi_host_alert_test	39.000s	35.430us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	19.464us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	84.543us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	84.543us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	122.326us	5	5	100.00
		spi_host_csr_rw	5.000s	16.463us	20	20	100.00
		spi_host_csr_aliasing	4.000s	26.738us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	21.446us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	122.326us	5	5	100.00
		spi_host_csr_rw	5.000s	16.463us	20	20	100.00
		spi_host_csr_aliasing	4.000s	26.738us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	21.446us	20	20	100.00
V2		TOTAL			687	690	99.57
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	251.359us	20	20	100.00
		spi_host_sec_cm	40.000s	1.477ms	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	251.359us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	7.450m	47.007ms	10	10	100.00
		TOTAL			837	840	99.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.20	96.78	93.27	98.69	94.36	73.07	100.00	97.29	90.42

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 2 failures:

Test spi_host_status_stall has 2 failures.

33.spi_host_status_stall.69167850432994818794687930561634802329131977129824133183612101900786602562384
Line 1377, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/33.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 1063102178 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 1063102178 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=1063102000 ps
  UVM_INFO @ 1063102178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.spi_host_status_stall.64631196254284813398312620402094208072954819371729475109413565544074077080272
Line 1379, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/36.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 1500160607 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 1500160607 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=1500161000 ps
  UVM_INFO @ 1500160607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_speed has 1 failures.
  - 39.spi_host_speed.11919415406653278627342239714344596035268770114581587971515397970799126286450
    Line 169, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/39.spi_host_speed/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```