SRAM_CTRL/MAIN Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: c4214fe

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.765m	787.840us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.110s	89.908us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.130s	12.963us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	4.190s	803.424us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.180s	13.849us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.780s	3.209ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.130s	12.963us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	13.849us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.825m	40.704ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.774m	48.892ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	21.657m	280.122ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.152m	6.926ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	35.920m	147.891ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	18.486m	31.317ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.687m	151.776ms	50	50	100.00
V2	executable	sram_ctrl_executable	24.101m	25.411ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.146m	2.194ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.980m	106.987ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.642m	3.186ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.737m	1.633ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.686m	15.189ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.574m	15.452ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.920s	3.060ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.833h	376.170ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.230s	38.397us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.390s	745.708us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.390s	745.708us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.110s	89.908us	5	5	100.00
		sram_ctrl_csr_rw	2.130s	12.963us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	13.849us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.290s	37.672us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.110s	89.908us	5	5	100.00
		sram_ctrl_csr_rw	2.130s	12.963us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	13.849us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.290s	37.672us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.091m	46.889ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.200s	2.213us	0	5	0.00
		sram_ctrl_tl_intg_err	5.000s	414.103us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.200s	2.213us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	5.000s	414.103us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.574m	15.452ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	22.574m	15.452ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.130s	12.963us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.101m	25.411ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.101m	25.411ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.101m	25.411ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.687m	151.776ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	11.090s	13.581ms	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.091m	46.889ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	16.060s	13.433ms	41	50	82.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.765m	787.840us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.765m	787.840us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.101m	25.411ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.200s	2.213us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.687m	151.776ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.200s	2.213us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.200s	2.213us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.765m	787.840us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.200s	2.213us	0	5	0.00
V2S		TOTAL			126	145	86.90
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.793m	38.708ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1171	1190	98.40

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.11	93.01	85.18	100.00	98.03	98.61	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 9 failures:
  • Test sram_ctrl_readback_err has 9 failures.

    • 11.sram_ctrl_readback_err.96703054042349031323869226999006924491916443097356028994799135497921054830561
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/11.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1992015727 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3d) != exp (0x7d)
        UVM_INFO @ 1992015727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 16.sram_ctrl_readback_err.82523878800923321399206218443439266008054237549180309491044316021829851694799
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/16.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2628228605 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x70) != exp (0x4c)
        UVM_INFO @ 2628228605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• Offending 'reqfifo_rvalid' has 5 failures:
  • Test sram_ctrl_mubi_enc_err has 5 failures.

    • 12.sram_ctrl_mubi_enc_err.69518868895362332049682765946262201818927169027271285976364993071844723619331
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 3482476284 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 3482476284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 17.sram_ctrl_mubi_enc_err.25902533450746166477835665911245567501186928112919782720879126486069698358285
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/17.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 8405504357 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 8405504357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.81776935293361881832182903551265872519420210452404753041813376014463890576143
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1717093 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1717093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.114426438046067780038212355491737386852555497138986905052885432065072367405981
      Line 97, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  10145219 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  10145219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.114546677078221110826167583553450399061114397981144934775903462552088461776600
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   2213350 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   2213350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---