SRAM_CTRL/RET Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: `c4214fe`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.414m	1.319ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.140s	18.234us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.160s	18.801us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.420s	148.204us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.200s	21.697us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.760s	218.818us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.160s	18.801us	20	20	100.00
		sram_ctrl_csr_aliasing	2.200s	21.697us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	16.580s	2.278ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.280s	189.469us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	21.901m	96.756ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.973m	6.324ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.766m	4.733ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.918m	20.612ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.310s	2.338ms	50	50	100.00
V2	executable	sram_ctrl_executable	27.853m	8.772ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.948m	783.241us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.881m	88.107ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.673m	513.270us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.820m	171.484us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.632m	1.114ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	20.248m	4.043ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.450s	52.566us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.611h	17.776ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.160s	32.981us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.950s	280.132us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.950s	280.132us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.140s	18.234us	5	5	100.00
		sram_ctrl_csr_rw	2.160s	18.801us	20	20	100.00
		sram_ctrl_csr_aliasing	2.200s	21.697us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.370s	34.286us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.140s	18.234us	5	5	100.00
		sram_ctrl_csr_rw	2.160s	18.801us	20	20	100.00
		sram_ctrl_csr_aliasing	2.200s	21.697us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.370s	34.286us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.800s	818.207us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.170s	6.897us	0	5	0.00
		sram_ctrl_tl_intg_err	4.220s	2.005ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.170s	6.897us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.220s	2.005ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	20.248m	4.043ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	20.248m	4.043ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.160s	18.801us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	27.853m	8.772ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	27.853m	8.772ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	27.853m	8.772ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.310s	2.338ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.770s	692.095us	42	50	84.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.800s	818.207us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.690s	95.442us	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.414m	1.319ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.414m	1.319ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	27.853m	8.772ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.170s	6.897us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.310s	2.338ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.170s	6.897us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.170s	6.897us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.414m	1.319ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.170s	6.897us	0	5	0.00
V2S		TOTAL			121	145	83.45
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	10.032m	8.507ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1164	1190	97.82

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	99.07	93.01	85.10	100.00	97.99	98.60	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 11 failures:
- Test sram_ctrl_readback_err has 11 failures.
  - 4.sram_ctrl_readback_err.30224324598934318841154620950822755583456067417617340966016078338661065693925
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  50724706 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x51) != exp (0x42)
  UVM_INFO @  50724706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.sram_ctrl_readback_err.74132622275561283640711896161712561002611124805050685823275317706014901504216
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  45889633 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1) != exp (0x8)
  UVM_INFO @  45889633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
Offending 'reqfifo_rvalid' has 8 failures:
- Test sram_ctrl_mubi_enc_err has 8 failures.
  - 5.sram_ctrl_mubi_enc_err.66886952304372108691400444086877836851171722521435611430085250163585225136485
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 122589335 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 122589335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.sram_ctrl_mubi_enc_err.85923757197217631947004583350221076646344855476123171140714436599126852049235
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 186307717 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 186307717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 5 failures:

Test sram_ctrl_sec_cm has 5 failures.

0.sram_ctrl_sec_cm.30992892679378885323901612510811501481246789733255016104735500469112500632099
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   6897266 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   6897266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.sram_ctrl_sec_cm.107610693454636102960364182697842548492128889729362908143476683724491224334176
Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   4491074 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   4491074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 11.sram_ctrl_csr_mem_rw_with_rand_reset.33439561720843949594813533171696360065925878733084174109609911686609437584518
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 246407292 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (6 [0x6] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @ 246407292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.sram_ctrl_csr_mem_rw_with_rand_reset.419003525618874099084120373290090575984820687970082094012757004921251215905
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  23946497 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  23946497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```