SYSRST_CTRL Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: `c4214fe`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	10.290s	2.112ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	11.740s	2.464ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	11.550s	2.416ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	10.390s	2.538ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	9.480s	4.027ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	9.510s	2.036ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	41.560s	76.546ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	12.040s	2.705ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	10.300s	2.072ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	9.510s	2.036ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.040s	2.705ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	6.468m	165.649ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	8.319m	206.875ms	93	100	93.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	11.840m	282.621ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	16.610s	5.948ms	48	50	96.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	11.910s	2.511ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	11.270s	2.210ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	4.529m	98.634ms	48	50	96.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	11.940s	2.609ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	3.576m	830.557ms	37	50	74.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	27.800s	41.321ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	7.698m	175.538ms	47	50	94.00
V2	alert_test	sysrst_ctrl_alert_test	9.780s	2.015ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	8.590s	2.016ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	11.070s	2.081ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	11.070s	2.081ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	9.480s	4.027ms	5	5	100.00
		sysrst_ctrl_csr_rw	9.510s	2.036ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.040s	2.705ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	34.230s	9.770ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	9.480s	4.027ms	5	5	100.00
		sysrst_ctrl_csr_rw	9.510s	2.036ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.040s	2.705ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	34.230s	9.770ms	20	20	100.00
V2		TOTAL			665	692	96.10
V2S	tl_intg_err	sysrst_ctrl_sec_cm	2.441m	42.009ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.785m	42.446ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.785m	42.446ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	26.540s	8.267ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			900	932	96.57

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.23	99.55	97.78	100.00	96.15	99.70	98.95	88.44

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 13 failures:

Test sysrst_ctrl_ultra_low_pwr has 7 failures.

3.sysrst_ctrl_ultra_low_pwr.78246959273687805130263361547016113482840860678259233293480546032804999050998
Line 381, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 5920059932 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 5920090543 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 5920090543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.sysrst_ctrl_ultra_low_pwr.36668939155017595324215579228897291052007278905631843741486248383479631161438
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 5391936731 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 5392151017 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 5392151017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test sysrst_ctrl_edge_detect has 2 failures.

13.sysrst_ctrl_edge_detect.64629417232079424611080944922024428160908563638638577220295722226245511589359
Line 385, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest/run.log

  UVM_ERROR @ 105368420288 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 105368540287 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 105368540287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.sysrst_ctrl_edge_detect.58022837012869014054252921217874087929414464027260206116902455213740925370262
Line 384, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest/run.log

  UVM_ERROR @ 2619240547 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 2619270546 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 2619270546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

14.sysrst_ctrl_stress_all_with_rand_reset.100766023211543699516326802147046192647220390568258782820711571691124919616535
Line 396, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7011518083 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 7011732369 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 7011732369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_stress_all has 3 failures.

19.sysrst_ctrl_stress_all.109950118582998028393116631704849214145545488431612474000884452791559770215198
Line 418, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 89714012517 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 89714044094 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 89714044094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.sysrst_ctrl_stress_all.51832946182264785391144596951642912685236977581962134076309621652119686437349
Line 390, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 12347563003 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 12347720898 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 12347720898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 7 failures:

Test sysrst_ctrl_ultra_low_pwr has 6 failures.

0.sysrst_ctrl_ultra_low_pwr.100944124593383697462728427056545434356517537335943383572594622024198383357826
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 148582559204 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 221530059204 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 221530059204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.sysrst_ctrl_ultra_low_pwr.68359503405887553698795271504706089279938804460546078518245340183356065522688
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2507823350 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2595323350 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 1008850323350 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 1008862698826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

26.sysrst_ctrl_stress_all_with_rand_reset.34610259679080145189463739760762200210371354159095876756434085571795176332477
Line 405, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10200977417 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 10243477417 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 10243477417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 4 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 4 failures.

6.sysrst_ctrl_combo_detect_with_pre_cond.45161445444523670939282342913894328692479401767415107784735981065117228932489
Line 444, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 78825191241 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 78825191241 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 78825191241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.sysrst_ctrl_combo_detect_with_pre_cond.49209529661457202240225118453704547964408287388167384191768834153039481412577
Line 400, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 27954107194 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 27954107194 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 27954107194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 2 failures:
- Test sysrst_ctrl_ec_pwr_on_rst has 2 failures.
  - 41.sysrst_ctrl_ec_pwr_on_rst.55070964029470952515721121056803211063472923081139827308956715548206085653368
    Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 4158211638 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 4158211638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 44.sysrst_ctrl_ec_pwr_on_rst.89582279200202957030463188290103945249005380453697975014982506443121732066945
    Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 3218147686 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 3218147686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

4.sysrst_ctrl_stress_all_with_rand_reset.69780141197745739627703326872931596284716970438755122069809752661955946618820
Line 401, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11146602214 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 11146602214 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:121) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_pwrb_in == inv_pwrb_out (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 11146602214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

12.sysrst_ctrl_combo_detect_with_pre_cond.96598165776698719995717353449012037434364908828794785642391900799663643117468
Line 415, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 40067946458 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4
  UVM_INFO @ 40082946458 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 50303873273 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x20
  UVM_INFO @ 50303916751 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xd
  UVM_INFO @ 50662946458 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0

UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:35) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

27.sysrst_ctrl_stress_all_with_rand_reset.12876856370909804041200285042754742970129895330492008334892799512697349523983
Line 384, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4038110686 ps: (sysrst_ctrl_pin_access_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 4038110686 ps: (sysrst_ctrl_pin_access_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.flash_wp_l_in == rdata_flash_wp_l_in (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4038110686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:36) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

48.sysrst_ctrl_stress_all_with_rand_reset.115515549219434646306318416405816484709902861467370642511020177836793635557497
Line 398, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4729687771 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 4729687771 ps: (sysrst_ctrl_pin_access_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key1_in == rdata_key1_in (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4729687771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

49.sysrst_ctrl_combo_detect_with_pre_cond.1524171276439871770621288922901549467087592362901381620067399828271219838524
Line 390, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13898935252 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 14003935252 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 14023935252 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_ERROR @ 14154023462 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 14154023462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

71.sysrst_ctrl_combo_detect_with_pre_cond.37690600419272185382160426776375023542201408532743821497706445778712245890973
Line 401, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/71.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 41340126132 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 51606835641 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x28
  UVM_INFO @ 51606918975 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2f
  UVM_INFO @ 54545275815 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
  UVM_INFO @ 54560126132 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 19