CHIP Simulation Results

Sunday June 15 2025 00:13:27 UTC

GitHub Revision: `c4214fe`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.581m	2.399ms	3	3	100.00
		chip_sw_example_rom	2.006m	2.623ms	3	3	100.00
		chip_sw_example_manufacturer	3.414m	3.375ms	3	3	100.00
		chip_sw_example_concurrency	3.664m	3.444ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	5.919m	7.828ms	5	5	100.00
V1	csr_rw	chip_csr_rw	9.585m	6.898ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	53.184m	43.438ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	1.364h	35.400ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	11.302m	10.450ms	6	20	30.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.364h	35.400ms	5	5	100.00
		chip_csr_rw	9.585m	6.898ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.050s	239.619us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.371m	4.182ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.371m	4.182ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.371m	4.182ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	8.011m	5.003ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	8.011m	5.003ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	7.218m	3.552ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	7.923m	4.561ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	7.543m	4.635ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	33.556m	13.144ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	35.998m	13.036ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	13.476m	8.485ms	5	5	100.00
V1		TOTAL			206	220	93.64
V2	chip_pin_mux	chip_padctrl_attributes	2.990m	6.136ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.990m	6.136ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.305m	2.492ms	2	3	66.67
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.441m	6.475ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	4.174m	4.460ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	13.217m	10.052ms	5	5	100.00
		chip_tap_straps_testunlock0	11.978m	8.727ms	5	5	100.00
		chip_tap_straps_rma	7.219m	6.135ms	5	5	100.00
		chip_tap_straps_prod	16.610m	12.462ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	3.363m	2.799ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	16.098m	8.744ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	9.505m	5.612ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	9.505m	5.612ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.869m	7.960ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	42.539m	20.123ms	0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.754m	4.451ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	12.763m	5.644ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.076h	18.513ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.249m	3.077ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	14.402m	6.243ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	3.649m	3.355ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	20.136m	8.656ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.179m	2.851ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	8.514m	5.540ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.276m	2.706ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.822m	3.128ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	9.879m	9.079ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.180m	5.412ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	3.835m	3.446ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.180m	5.412ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.663m	2.955ms	3	3	100.00
		chip_sw_aes_smoketest	3.761m	3.079ms	3	3	100.00
		chip_sw_aon_timer_smoketest	4.293m	3.213ms	3	3	100.00
		chip_sw_clkmgr_smoketest	3.133m	3.135ms	3	3	100.00
		chip_sw_csrng_smoketest	3.087m	2.719ms	3	3	100.00
		chip_sw_entropy_src_smoketest	6.952m	3.737ms	3	3	100.00
		chip_sw_gpio_smoketest	3.835m	3.586ms	3	3	100.00
		chip_sw_hmac_smoketest	3.794m	3.335ms	3	3	100.00
		chip_sw_kmac_smoketest	2.963m	2.653ms	3	3	100.00
		chip_sw_otbn_smoketest	21.286m	8.287ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	3.849m	5.102ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.414m	4.925ms	3	3	100.00
		chip_sw_rv_plic_smoketest	2.872m	3.193ms	3	3	100.00
		chip_sw_rv_timer_smoketest	3.743m	3.444ms	3	3	100.00
		chip_sw_rstmgr_smoketest	3.428m	2.755ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	3.828m	2.974ms	3	3	100.00
		chip_sw_uart_smoketest	2.741m	3.284ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	3.578m	2.835ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	7.941m	5.374ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.952h	60.159ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	57.872m	15.064ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	3.941m	6.543ms	2	3	66.67
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	4.006m	2.934ms	0	3	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.599m	3.031ms	0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.636h	53.821ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.952h	55.624ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	6.331m	4.236ms	4	30	13.33
V2	tl_d_illegal_access	chip_tl_errors	6.331m	4.236ms	4	30	13.33
V2	tl_d_outstanding_access	chip_csr_aliasing	1.364h	35.400ms	5	5	100.00
		chip_same_csr_outstanding	56.938m	30.275ms	20	20	100.00
		chip_csr_hw_reset	5.919m	7.828ms	5	5	100.00
		chip_csr_rw	9.585m	6.898ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.364h	35.400ms	5	5	100.00
		chip_same_csr_outstanding	56.938m	30.275ms	20	20	100.00
		chip_csr_hw_reset	5.919m	7.828ms	5	5	100.00
		chip_csr_rw	9.585m	6.898ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.135m	2.088ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.280s	56.357us	100	100	100.00
		xbar_smoke_large_delays	1.933m	10.241ms	100	100	100.00
		xbar_smoke_slow_rsp	1.621m	5.825ms	100	100	100.00
		xbar_random_zero_delays	45.810s	532.853us	100	100	100.00
		xbar_random_large_delays	7.523m	49.390ms	100	100	100.00
		xbar_random_slow_rsp	7.643m	34.725ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	51.790s	1.295ms	100	100	100.00
		xbar_error_and_unmapped_addr	45.830s	1.458ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.151m	2.605ms	100	100	100.00
		xbar_error_and_unmapped_addr	45.830s	1.458ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.873m	3.782ms	100	100	100.00
		xbar_access_same_device_slow_rsp	15.697m	83.601ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.305m	2.794ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	9.623m	25.743ms	100	100	100.00
		xbar_stress_all_with_error	7.638m	19.027ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	8.576m	7.018ms	100	100	100.00
		xbar_stress_all_with_reset_error	11.392m	24.815ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	57.872m	15.064ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	54.253m	27.635ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	56.508m	14.970ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	20.973s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	1.203m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	48.422s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	58.740s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	31.097s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	30.571s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	22.490s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	29.889s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	21.829s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	46.526s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	18.299s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	59.051s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	30.010s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	21.148s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	22.046s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	28.542s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	31.238s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	21.293s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	19.097s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	42.274s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	20.055s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	58.952s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	43.274s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	59.360s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	48.695s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	35.041s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	1.067m		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	26.070s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	32.105s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	34.554s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	44.109m	11.401ms	2	3	66.67
		rom_e2e_asm_init_dev	1.001h	15.930ms	2	3	66.67
		rom_e2e_asm_init_prod	59.879m	16.013ms	2	3	66.67
		rom_e2e_asm_init_prod_end	59.535m	15.484ms	2	3	66.67
		rom_e2e_asm_init_rma	57.281m	14.615ms	2	3	66.67
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	59.314m	14.764ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	56.188m	15.013ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	57.906m	14.883ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.014h	15.880ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.428m	2.637ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.249m	3.077ms	3	3	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.953m	2.706ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.974m	2.456ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	27.863m	10.548ms	3	3	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.270m	2.744ms	0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	7.398m	5.643ms	3	3	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	9.440m	6.288ms	93	100	93.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	11.583m	5.217ms	3	3	100.00
		chip_plic_all_irqs_10	5.843m	3.270ms	3	3	100.00
		chip_plic_all_irqs_20	7.976m	3.993ms	3	3	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.075m	3.446ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	20.576m	10.998ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	6.939m	5.561ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	3.770m	3.067ms	0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	14.487m	12.540ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	23.942m	9.114ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	20.803m	7.771ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	15.665m	7.736ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.500h	255.738ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	5.019m	4.309ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.849m	5.102ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	5.019m	4.309ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.115m	8.257ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.115m	8.257ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.424m	8.346ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.989m	5.082ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	11.669m	5.802ms	3	3	100.00
		chip_sw_aes_idle	2.974m	2.456ms	3	3	100.00
		chip_sw_hmac_enc_idle	3.517m	2.837ms	3	3	100.00
		chip_sw_kmac_idle	3.319m	2.634ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	5.944m	5.206ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	5.630m	4.481ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	7.081m	5.650ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	6.451m	5.096ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	18.420m	11.247ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	7.193m	3.642ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	7.337m	4.179ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	8.109m	4.117ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	7.206m	4.360ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	8.417m	4.740ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.408m	4.041ms	3	3	100.00
		chip_sw_ast_clk_outputs	11.869m	7.960ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.518m	9.863ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	8.109m	4.117ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	7.206m	4.360ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.754m	4.451ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	12.763m	5.644ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.076h	18.513ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.249m	3.077ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	14.402m	6.243ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	3.649m	3.355ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	20.136m	8.656ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.179m	2.851ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	8.514m	5.540ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.276m	2.706ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.652m	2.771ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.976m	4.586ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	13.065m	7.086ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.235h	23.967ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	3.114m	3.596ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	3.009m	2.695ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	23.527m	13.242ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.119m	2.829ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	6.658m	5.354ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	26.448m	25.578ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	4.357h	134.395ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.869m	7.960ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	7.760m	4.564ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.253m	3.213ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	9.440m	6.288ms	93	100	93.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	23.942m	9.114ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	18.614m	7.685ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.036m	2.304ms	0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	7.077m	4.973ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.301m	2.619ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.600h	29.842ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	3.249m	2.852ms	3	3	100.00
		chip_sw_edn_entropy_reqs	13.487m	7.325ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.249m	2.852ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	18.614m	7.685ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	3.162m	2.866ms	3	3	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	29.061m	19.967ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	12.594m	5.979ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	12.763m	5.644ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	7.171m	3.644ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.754m	4.451ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.210h	44.908ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	29.061m	19.967ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	4.149m	3.504ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	32.987m	12.167ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.933m	4.461ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.210h	44.908ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.933m	4.461ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.933m	4.461ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.933m	4.461ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.933m	4.461ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	9.440m	6.288ms	93	100	93.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	5.190m	11.633ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	12.085m	5.497ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.599m	4.542ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.599m	4.542ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.061m	2.541ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	3.649m	3.355ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.517m	2.837ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	4.321m	3.621ms	3	3	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	7.368m	4.160ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.774m	6.246ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	8.987m	5.161ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	8.373m	5.269ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	6.710m	3.860ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	32.987m	12.167ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	20.136m	8.656ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	22.924m	10.429ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	27.863m	10.548ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	49.836m	14.337ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.571m	3.043ms	3	3	100.00
		chip_sw_kmac_mode_kmac	4.063m	3.590ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.179m	2.851ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	32.987m	12.167ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.678m	12.750ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	3.089m	2.704ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	14.208m	6.749ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.319m	2.634ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	7.398m	5.643ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	13.217m	10.052ms	5	5	100.00
		chip_tap_straps_rma	7.219m	6.135ms	5	5	100.00
		chip_tap_straps_prod	16.610m	12.462ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.874m	2.913ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.678m	12.750ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.678m	12.750ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.678m	12.750ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	23.249m	9.862ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.933m	4.461ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.210h	44.908ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.027m	3.734ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	11.454m	7.257ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	12.225m	8.498ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	10.461m	7.604ms	3	3	100.00
		chip_sw_lc_ctrl_transition	12.678m	12.750ms	15	15	100.00
		chip_sw_keymgr_key_derivation	32.987m	12.167ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	6.548m	8.775ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	9.010m	6.908ms	3	3	100.00
		chip_prim_tl_access	5.190m	11.633ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.518m	9.863ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	7.193m	3.642ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	7.337m	4.179ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	8.109m	4.117ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	7.206m	4.360ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	8.417m	4.740ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.408m	4.041ms	3	3	100.00
		chip_tap_straps_dev	13.217m	10.052ms	5	5	100.00
		chip_tap_straps_rma	7.219m	6.135ms	5	5	100.00
		chip_tap_straps_prod	16.610m	12.462ms	5	5	100.00
		chip_rv_dm_lc_disabled	8.515m	17.132ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.576m	2.947ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.300m	2.898ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.510m	3.313ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.398m	2.931ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	27.840m	22.880ms	3	3	100.00
		chip_rv_dm_lc_disabled	8.515m	17.132ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.337h	47.769ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.417h	50.408ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	12.109m	8.750ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.422h	45.489ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	27.840m	22.880ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.435m	2.609ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.228m	2.523ms	3	3	100.00
		rom_volatile_raw_unlock	1.543m	2.787ms	2	3	66.67
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	1.128h	16.952ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.076h	18.513ms	3	3	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	11.669m	5.802ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	11.669m	5.802ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	11.669m	5.802ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	6.521m	3.552ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.678m	12.750ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	29.061m	19.967ms	3	3	100.00
		chip_sw_otbn_mem_scramble	6.521m	3.552ms	3	3	100.00
		chip_sw_keymgr_key_derivation	32.987m	12.167ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	7.891m	4.542ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.400m	2.372ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	29.061m	19.967ms	3	3	100.00
		chip_sw_otbn_mem_scramble	6.521m	3.552ms	3	3	100.00
		chip_sw_keymgr_key_derivation	32.987m	12.167ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	7.891m	4.542ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.400m	2.372ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.678m	12.750ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	6.498m	5.013ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.874m	2.913ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.027m	3.734ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	11.454m	7.257ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	12.225m	8.498ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	10.461m	7.604ms	3	3	100.00
		chip_sw_lc_ctrl_transition	12.678m	12.750ms	15	15	100.00
		chip_prim_tl_access	5.190m	11.633ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.190m	11.633ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	20.213m	8.617ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.694m	9.743ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	22.770m	29.601ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	6.912m	8.136ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	9.293m	8.602ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	9.760m	8.437ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	23.651m	24.452ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	15.494m	13.954ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	10.115m	8.257ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	18.926m	11.358ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.848m	3.611ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.694m	9.743ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	6.154m	4.307ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	47.304m	34.744ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	6.464m	5.897ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.184m	6.065ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	28.634m	20.088ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	17.367m	8.681ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	20.718m	12.718ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	27.380m	20.789ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.297m	3.095ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	9.440m	6.288ms	93	100	93.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	6.548m	8.775ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	6.548m	8.775ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	20.718m	12.718ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	28.634m	20.088ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	5.848m	3.611ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	3.849m	5.102ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.832m	4.257ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	5.906m	4.045ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.821m	4.254ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	20.576m	10.998ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.275m	2.430ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	9.440m	6.288ms	93	100	93.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	20.803m	7.771ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	9.234m	4.979ms	3	3	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	10.584m	4.843ms	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.771m	2.695ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.400m	2.372ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	5.906m	4.045ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	5.906m	4.045ms	0	3	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	33.333m	19.855ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	20.008m	13.517ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.832m	4.257ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	6.817m	5.135ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	6.948m	6.089ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	7.219m	6.135ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	8.515m	17.132ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	11.583m	5.217ms	3	3	100.00
		chip_plic_all_irqs_10	5.843m	3.270ms	3	3	100.00
		chip_plic_all_irqs_20	7.976m	3.993ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.802m	3.452ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.891m	3.490ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	57.872m	15.064ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	11.817m	7.944ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.181m	3.336ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	4.072m	3.091ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.885m	3.531ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.891m	4.542ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	8.514m	5.540ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	8.164m	7.871ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.812m	7.300ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.010m	6.908ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	9.440m	6.288ms	93	100	93.00
		chip_sw_data_integrity_escalation	9.505m	5.612ms	6	6	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	17.367m	8.681ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	23.800m	23.833ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	3.096m	2.669ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	4.821m	3.269ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	7.605m	4.995ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	23.800m	23.833ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	23.800m	23.833ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	51.383m	20.972ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	51.383m	20.972ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.897m	6.174ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.763m	3.477ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.305m	3.039ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.261m	3.951ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.333m	3.240ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	20.091m	8.399ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.726h	31.068ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	32.519m	12.454ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.087m	3.180ms	1	1	100.00
V2		TOTAL			2472	2657	93.04
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.740m	3.166ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.244m	2.734ms	2	3	66.67
V2S		TOTAL			5	6	83.33
V3	chip_sw_coremark	chip_sw_coremark	3.852h	71.824ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	17.127m	6.123ms	2	3	66.67
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	22.981m	11.532ms	1	1	100.00
		rom_e2e_jtag_debug_dev	23.816m	11.909ms	1	1	100.00
		rom_e2e_jtag_debug_rma	24.926m	11.993ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.524m		0	1	0.00
		rom_e2e_jtag_inject_dev	3.127m		0	1	0.00
		rom_e2e_jtag_inject_rma	1.174m		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	24.153s		0	3	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	10.982m	5.291ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.740m	3.092ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	16.660m	5.757ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	19.162m	7.145ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	4.163m	2.097ms	3	3	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	11.899m	4.594ms	3	3	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.377m	2.920ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	3.885m	5.211ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	6.645m	7.104ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.940m	4.694ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	20.718m	12.718ms	3	3	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	22.981m	11.532ms	1	1	100.00
		rom_e2e_jtag_debug_dev	23.816m	11.909ms	1	1	100.00
		rom_e2e_jtag_debug_rma	24.926m	11.993ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	8.341m	5.272ms	3	3	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	9.440m	6.288ms	93	100	93.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.918h	38.334ms	2	3	66.67
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.918h	38.334ms	2	3	66.67
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.407m	2.850ms	3	3	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	8.011m	5.003ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.050h	18.977ms	1	1	100.00
V3		TOTAL			43	51	84.31
	Unmapped tests	chip_sival_flash_info_access	2.991m	2.956ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	8.470m	5.860ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.775m	2.407ms	3	3	100.00
		chip_sw_otp_ctrl_descrambling	4.356m	3.293ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	5.341m	4.354ms	2	3	66.67
		chip_sw_pwrmgr_sleep_wake_5_bug	20.173s		0	3	0.00
		chip_sw_flash_ctrl_write_clear	3.921m	3.646ms	3	3	100.00
		TOTAL			2743	2955	92.83

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.33	94.78	93.68	92.30	--	94.41	97.51	99.33

Failure Buckets

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 89 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 89 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.108010268429573898276479031262410903782285906901614415351926106056419123732797
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3158.286564 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3158.286564 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_alert_handler_lpg_sleep_mode_alerts.26547525914783642101624078624491951989553621849314431620000833916328677959054
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3124.654570 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3124.654570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 87 more failures.

Job returned non-zero exit code has 46 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 3 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.72411262903177167193132759618824184398144230866222985218427553737323845803586
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.199s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_pwrmgr_sleep_wake_5_bug.34052835952444810541471376436560330550202607013592380348664678067411587235889
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 2.020s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.8278721429375162079309694228910169133101790443390828297567958726125607328189
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

      File "/nightly/runs/opentitan/rules/bitstreams.bzl", line 70, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:64:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 7.001s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_dev.108422509574377594466605338511009697325137762882596880245517294093796392542176
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:64:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26451 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 57.141s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod.89293880663021693113485614876428849460367349612644783471115137467102809832572
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:64:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26451 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 32.638s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.102863633626092138882789390124877124409846871945515678237676863048135233129078
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log

      File "/nightly/runs/opentitan/rules/bitstreams.bzl", line 70, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:76:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 44.522s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 37 more tests.

UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 6 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 9.chip_sw_alert_handler_lpg_sleep_mode_alerts.45899912155801310548958682314268899710979048278181125572844984295120251587047
    Line 402, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_FATAL @  10.260001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_all_escalation_resets has 5 failures.
  - 22.chip_sw_all_escalation_resets.14773239479277345950129800115873834869269662388459357372346688085232468197177
    Line 399, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.160001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 54.chip_sw_all_escalation_resets.63586051343712362125028345516249141604231589073872242272536421943504740696130
    Line 410, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.180001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
Job timed out after * minutes has 4 failures:
- Test chip_sw_rv_timer_systick_test has 1 failures.
  - 0.chip_sw_rv_timer_systick_test.103055458093385036963988002475080117915082084473062221630258289098672697183347
    Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job timed out after 120 minutes
```
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 3 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.110045625896184860278851712582515249674124387740207682219181631967650758653072
    Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.67089099044691542972044339737485741284118054116448481890271626091341735228722
    Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
- Test chip_sw_spi_device_pass_through_collision has 3 failures.
  - 0.chip_sw_spi_device_pass_through_collision.6309191111910717835604699360610047746959791090385087324458022580255421974546
    Line 735, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2891.019430 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2891.019430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_spi_device_pass_through_collision.77628484389082014899678627965320193264547330968259166961766512013172347565382
    Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2375.488484 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2375.488484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 3 failures:
- Test chip_sw_alert_test has 3 failures.
  - 0.chip_sw_alert_test.12290236290901269738630393455039620185059851564645051086924716925343912882597
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3097.020888 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3097.020888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_alert_test.47952508265988511388198541840622775047365589141638233105806477290332267439879
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2743.525802 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2743.525802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 3 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 3 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.97809371413297645238046971054078741404855315976229170251528216148076935852368
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 3090.409633 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 3090.409633 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_csrng_fuse_en_sw_app_read_test.58097223407601926454256018691495073268166324045417584391226757079255491422028
    Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2608.352031 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2608.352031 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 3 failures:

Test chip_sw_power_idle_load has 3 failures.

0.chip_sw_power_idle_load.54879290735226479542850705277271645053754177305187494907724320127403306183172
Line 446, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log

  UVM_ERROR @ 3613.456000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3613.456000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_power_idle_load.54607306357387857523141178262116390244258216361400228785799826568024950350541
Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest/run.log

  UVM_ERROR @ 3490.878000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3490.878000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 3 failures:

Test chip_sw_power_sleep_load has 3 failures.

0.chip_sw_power_sleep_load.12235392709096491663763690912257911653259577661103191902749314616835233265036
Line 456, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log

  UVM_ERROR @ 3003.592000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3003.592000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_power_sleep_load.12308533503534849031253606729642523923414962841535185777769414415814399244658
Line 424, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest/run.log

  UVM_ERROR @ 3031.229500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3031.229500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 3 failures:
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.115588046153801130937943707449429728104188825933878429756210583653942956156010
    Line 451, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 18343.442122 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 18343.442122 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_ast_clk_rst_inputs.40242879062379914114461812595781822197534597812780641139495322695850272966591
    Line 453, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 20122.646819 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 20122.646819 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32439) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_tl_errors has 2 failures.

2.chip_tl_errors.81946692630502759470656609376347814114326316921243327297090262323211102696289
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2337.853798 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32439) { a_addr: 'h10524  a_data: 'h452786e8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h4  a_user: 'h186be  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2337.853798 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.chip_tl_errors.26357125321115699840191805781357491424542763401445468969611925432818567397814
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2279.580250 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32439) { a_addr: 'h10594  a_data: 'hd976cae6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h18a60  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2279.580250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32549) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_csr_mem_rw_with_rand_reset has 2 failures.

5.chip_csr_mem_rw_with_rand_reset.865725757261577686582474005286253474202341321977320389108443862461603962563
Line 235, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2575.044472 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32549) { a_addr: 'h10790  a_data: 'hddb924d1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h24  a_opcode: 'h4  a_user: 'h18d94  d_param: 'h0  d_source: 'h24  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2575.044472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.chip_csr_mem_rw_with_rand_reset.48096021487929219608468223708533631769391861529777362779981546392406608169894
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1992.308600 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32549) { a_addr: 'h104dc  a_data: 'h4bb27875  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4  a_opcode: 'h4  a_user: 'h1b148  d_param: 'h0  d_source: 'h4  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1992.308600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
- Test chip_sw_all_escalation_resets has 2 failures.
  - 8.chip_sw_all_escalation_resets.33135207877156785477582965556950667893426808094726783800848573504448005509755
    Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2250.522926 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2250.522926 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 87.chip_sw_all_escalation_resets.5105253198632001840223246285722418314854942372001925748615247452337825889224
    Line 536, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/87.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2792.977024 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2792.977024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@106531) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.12226588671430756769193716563864731481058948616196064868918194867044207456230
Line 430, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4136.717976 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@106531) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4136.717976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34317) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.91848449022709347284950607234287697120681787134100742955552036043916015822803
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2763.616158 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34317) { a_addr: 'h106f0  a_data: 'hf1d9088e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1badf  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2763.616158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.82664989132589408104999635999584248728651897942240452230809525837568481617862
    Line 432, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2734.166128 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2734.166128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31951) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.36254430084796045012201343962323113773198123071082653777360183960617784753732
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2401.114562 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31951) { a_addr: 'h10704  a_data: 'he0e6a5c1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h4  a_user: 'h19560  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2401.114562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@109155) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

1.chip_sw_rstmgr_cpu_info.73322868840118580957369406484220242263698973343239438197900504108748861130208
Line 442, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4045.482722 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@109155) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4045.482722 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34727) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

1.chip_tl_errors.108372209597703299907271644430712296827271996493940305285204201524982068760682
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2563.239720 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34727) { a_addr: 'h1035c  a_data: 'h84942661  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h4  a_user: 'h19eec  d_param: 'h0  d_source: 'h2e  d_data: 'h100073  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd04  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2563.239720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 1.chip_sw_power_virus.102795115774913711115556076278695502162673725224433410389098329554327514549472
    Line 502, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3997.407858 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3997.407858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31895) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

1.chip_csr_mem_rw_with_rand_reset.59392951792730348809301782998931687020504790111030856228132193885780712509520
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1967.229638 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31895) { a_addr: 'h10480  a_data: 'h16eb2588  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h1a568  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1967.229638 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 2.chip_sw_sleep_pin_mio_dio_val.29775806994952142370490811553157465001803968706209514237704194441484168792971
    Line 553, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3238.999000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3238.999000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@108691) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

2.chip_sw_rstmgr_cpu_info.94959292844594791421460135236789168640230671374152975660384021181181431905926
Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3404.723530 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@108691) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3404.723530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 2.chip_sw_pwrmgr_lowpower_cancel.97927276552119014840719155017901952463606048880204361118638397499395476799327
    Line 420, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3192.545276 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3192.545276 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32369) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

2.chip_csr_mem_rw_with_rand_reset.114407142941440143145215350806713355877772906557798961386141945349937080964657
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2644.867752 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32369) { a_addr: 'h104b0  a_data: 'h79f58574  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h4  a_user: 'h1996d  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2644.867752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33811) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

3.chip_tl_errors.2411494658666491245187095514601152520786690144788613211102858372087632717551
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2624.938254 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33811) { a_addr: 'h1043c  a_data: 'h464ccbd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h4  a_user: 'h1b1f6  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2624.938254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32801) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

3.chip_csr_mem_rw_with_rand_reset.61899409498191610893275300728080179564011697682088246626006794458589047796924
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2383.032680 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32801) { a_addr: 'h10454  a_data: 'hbae631e8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h1956a  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2383.032680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33701) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

4.chip_tl_errors.95299237650811806419871399605328212031613519316911455044569255581531749077513
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2525.971016 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33701) { a_addr: 'h1060c  a_data: 'h633d33c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h4  a_user: 'h186dc  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2525.971016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34071) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

4.chip_csr_mem_rw_with_rand_reset.65898928177943162656089634887472730922276627161159110439324221073268725193582
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2547.963240 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34071) { a_addr: 'h1063c  a_data: 'h515c1538  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h4  a_user: 'h1ba89  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2547.963240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38413) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

5.chip_tl_errors.50790545469185259035825085548663263405730017229563542885655047890453434245899
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2322.963224 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38413) { a_addr: 'h104d8  a_data: 'h48af5edf  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h4  a_user: 'h1bdd7  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2322.963224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35651) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

6.chip_tl_errors.103626307385940366582376843847659946867893389998574353010696018612642652411379
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2503.491968 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35651) { a_addr: 'h1078c  a_data: 'h7ae5556a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h4  a_user: 'h1b131  d_param: 'h0  d_source: 'h2d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2503.491968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32015) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

8.chip_tl_errors.71776254456041130519669142480539421769766543464200686843123190204933361777016
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2259.998412 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32015) { a_addr: 'h105d4  a_data: 'hfc6a7316  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h4  a_user: 'h1a2c5  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2259.998412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35595) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

9.chip_tl_errors.72940707273497641696215730304540629254598735559578074829535151170267475806590
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1875.707300 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35595) { a_addr: 'h10364  a_data: 'hf7991531  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h4  a_user: 'h1b614  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1875.707300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31891) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

9.chip_csr_mem_rw_with_rand_reset.88182971526623747851949861192682399791548976856829881690677311270463146766264
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1744.256460 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31891) { a_addr: 'h105d0  a_data: 'ha9bd303f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h4  a_user: 'h1ae0d  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1744.256460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31731) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

10.chip_tl_errors.50382167634907677063564504708995031062118778786323031893126750628452562123221
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2439.650080 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31731) { a_addr: 'h10480  a_data: 'he35d5a72  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h17  a_opcode: 'h4  a_user: 'h1a52c  d_param: 'h0  d_source: 'h17  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2439.650080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33175) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

10.chip_csr_mem_rw_with_rand_reset.50583453756094903249415513370026965613324109056476548413701843916986851418554
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2106.937256 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33175) { a_addr: 'h105ec  a_data: 'h3d183bcb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h4  a_user: 'h18a4b  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2106.937256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32849) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

11.chip_csr_mem_rw_with_rand_reset.76904562753541204056320286972153688076043646744128457761473329179960125403684
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2215.044120 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32849) { a_addr: 'h10508  a_data: 'h92135b96  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h1865a  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2215.044120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32815) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

12.chip_tl_errors.89902665881644319267300939113047797895187534333969788414992080258046995772901
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2199.305248 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32815) { a_addr: 'h10414  a_data: 'he8b1c89a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h4  a_user: 'h1bd97  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2199.305248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32711) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

12.chip_csr_mem_rw_with_rand_reset.103108460836245455226581170250497484491981342986546161057510951130607544147279
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2272.761032 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32711) { a_addr: 'h10790  a_data: 'h8d263275  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h4  a_user: 'h18db0  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2272.761032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32095) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

13.chip_csr_mem_rw_with_rand_reset.12962891719043061139354937655045237419567899957721359961549573428912759035843
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2252.488184 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32095) { a_addr: 'h105c4  a_data: 'hf2ff5590  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h24  a_opcode: 'h4  a_user: 'h18663  d_param: 'h0  d_source: 'h24  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2252.488184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32201) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

14.chip_csr_mem_rw_with_rand_reset.102182654830603465735306735922330880444039813851063430469354238800748676270961
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2343.774800 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32201) { a_addr: 'h104e8  a_data: 'hff36ca9e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2a  a_opcode: 'h4  a_user: 'h18198  d_param: 'h0  d_source: 'h2a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2343.774800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35795) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

15.chip_tl_errors.111894410368992457098415580846178749563837867752713714500298833792356114056606
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2609.238058 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35795) { a_addr: 'h10580  a_data: 'hfefbd148  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h4  a_user: 'h1a201  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2609.238058 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34893) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

16.chip_tl_errors.63962439042592233151250176028294612780503244430100625646114421788311980299254
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2508.621196 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34893) { a_addr: 'h105c8  a_data: 'hca80ee94  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h4  a_user: 'h19e38  d_param: 'h0  d_source: 'h2d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2508.621196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34227) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

18.chip_tl_errors.113582842948965656060589057018544773898912196053405111798190369011850019824020
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2209.701844 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34227) { a_addr: 'h10518  a_data: 'h8f980db5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h1a2ee  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2209.701844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34169) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

19.chip_tl_errors.33262416791247670269546358292592586380182382815358910537379649826751582158435
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2861.160120 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34169) { a_addr: 'h1033c  a_data: 'h6a3f00af  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h4  a_user: 'h1aef9  d_param: 'h0  d_source: 'h3  d_data: 'h517  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd10  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2861.160120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@213727) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

19.chip_csr_mem_rw_with_rand_reset.18761674811960605364755619931045614414073219717622882629005671645230731306690
Line 244, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 5225.463739 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@213727) { a_addr: 'h10738  a_data: 'h5e668d35  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h17  a_opcode: 'h4  a_user: 'h1b105  d_param: 'h0  d_source: 'h17  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5225.463739 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33545) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

20.chip_tl_errors.112645823519598444820771378892059995215596910400040040605454100569515992677015
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2300.276390 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33545) { a_addr: 'h10374  a_data: 'hbedc3c76  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1a  a_opcode: 'h4  a_user: 'h192fa  d_param: 'h0  d_source: 'h1a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2300.276390 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@284369) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

21.chip_tl_errors.43076415458054789977366680151157681040726524534760770000303175027251552857570
Line 220, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4099.220950 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@284369) { a_addr: 'h106d0  a_data: 'hcba438fc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4  a_opcode: 'h4  a_user: 'h1a27b  d_param: 'h0  d_source: 'h4  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4099.220950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40073) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

22.chip_tl_errors.50305196024100635007033628429667482656529885114896624008039858189642114775243
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2339.594650 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40073) { a_addr: 'h107e0  a_data: 'hfc3ab222  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h19937  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2339.594650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

23.chip_tl_errors.39889633238758515750613608335320548824471475891865470021352283020181426225527
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2606.386292 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33337) { a_addr: 'h106ac  a_data: 'hfa719107  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3b  a_opcode: 'h4  a_user: 'h1aee7  d_param: 'h0  d_source: 'h3b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2606.386292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38421) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

24.chip_tl_errors.56412001722696394233463176508851058554236012594736556552260487671057575852076
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2144.262024 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38421) { a_addr: 'h10698  a_data: 'hfd4e7cde  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h4  a_user: 'h19e29  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2144.262024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33705) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

25.chip_tl_errors.66636386992345693821363435516293091607017244764376347660882000781763029798826
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2489.648184 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33705) { a_addr: 'h104c4  a_data: 'h20daae8a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h1814c  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2489.648184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37407) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

26.chip_tl_errors.8312296940166090599439813211112701422598635172463096999013743479147530204491
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2374.924184 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37407) { a_addr: 'h10450  a_data: 'h3df33ee8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h199e2  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2374.924184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33723) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

27.chip_tl_errors.76325440204675348345038517393966664112735980659280907651383377689391234477377
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1742.308500 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33723) { a_addr: 'h10784  a_data: 'h3245d787  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h4  a_user: 'h1a5f9  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1742.308500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@140853) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

28.chip_tl_errors.82708840451591292154763196197941675392960253429040081220831452323732705781486
Line 220, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3569.331504 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@140853) { a_addr: 'h106ac  a_data: 'hbcdf158a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h20  a_opcode: 'h4  a_user: 'h1aebb  d_param: 'h0  d_source: 'h20  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3569.331504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35869) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

29.chip_tl_errors.100936868444064792160606423592635230743695921042513771127826023162685399356
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1814.658728 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35869) { a_addr: 'h106ec  a_data: 'hdca2396c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h4  a_user: 'h18610  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1814.658728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---