ADC_CTRL Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	22.310s	5.779ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	5.310s	1.116ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	4.220s	518.533us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	51.800s	22.073ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	7.590s	999.239us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	4.020s	510.442us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	4.220s	518.533us	20	20	100.00
		adc_ctrl_csr_aliasing	7.590s	999.239us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	21.913m	485.677ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	22.075m	498.800ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	15.393m	488.414ms	49	50	98.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.975m	493.423ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	29.736m	686.149ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.184m	590.648ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	18.039m	352.229ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	24.543m	2.000s	32	50	64.00
V2	poweron_counter	adc_ctrl_poweron_counter	20.450s	5.324ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.451m	45.572ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	7.107m	144.432ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	56.437m	1.662s	47	50	94.00
V2	alert_test	adc_ctrl_alert_test	3.640s	482.676us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	4.080s	526.408us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.930s	447.297us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.930s	447.297us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	5.310s	1.116ms	5	5	100.00
		adc_ctrl_csr_rw	4.220s	518.533us	20	20	100.00
		adc_ctrl_csr_aliasing	7.590s	999.239us	5	5	100.00
		adc_ctrl_same_csr_outstanding	29.440s	5.243ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	5.310s	1.116ms	5	5	100.00
		adc_ctrl_csr_rw	4.220s	518.533us	20	20	100.00
		adc_ctrl_csr_aliasing	7.590s	999.239us	5	5	100.00
		adc_ctrl_same_csr_outstanding	29.440s	5.243ms	20	20	100.00
V2		TOTAL			718	740	97.03
V2S	tl_intg_err	adc_ctrl_sec_cm	13.820s	4.173ms	5	5	100.00
		adc_ctrl_tl_intg_err	27.950s	7.890ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	27.950s	7.890ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	1.050h	10.000s	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			896	920	97.39

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.40	99.05	96.03	100.00	100.00	98.64	97.57	90.51

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 16 failures:
- Test adc_ctrl_clock_gating has 14 failures.
  - 4.adc_ctrl_clock_gating.98978777347072623390550597614229685152910896538176049078933721759521245978325
    Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.adc_ctrl_clock_gating.89330495585361440168057081359387556300093234168051296477188352129759049392257
    Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.
- Test adc_ctrl_stress_all has 1 failures.
  - 33.adc_ctrl_stress_all.100963504855049556195393203000176681574458992750706249105329120176041996110971
    Line 165, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 35.adc_ctrl_stress_all_with_rand_reset.56286306455772316972437703964787308560589557218426322237181162863094686146851
    Line 181, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 4 failures:
- Test adc_ctrl_clock_gating has 3 failures.
  - 18.adc_ctrl_clock_gating.97002390344779600227906229679164896186038535000323620993310331392000824265081
    Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 2339386082 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 2339386082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 35.adc_ctrl_clock_gating.102376155853770454403203782560072567700552765318956949306961636748275073936199
    Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/35.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 3737954886 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 3737954886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.adc_ctrl_stress_all_with_rand_reset.32263976089272699933666130444297565747201465997961321838635045067303310694034
    Line 152, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5135799666 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 5135799666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 4 failures:

Test adc_ctrl_filters_interrupt has 1 failures.

23.adc_ctrl_filters_interrupt.39749526099087264673715732206454752524371623704364145360982520142524053736268
Line 162, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 241899492361 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 241899492361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all has 2 failures.

36.adc_ctrl_stress_all.101996439202559169974811856206813226805397461849230684841286038460173593273262
Line 165, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 248097556929 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 248097556929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.adc_ctrl_stress_all.97157138279146515067996910368070860373731171768311097791345976652397758238884
Line 252, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 460698643402 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 460698643402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_clock_gating has 1 failures.

47.adc_ctrl_clock_gating.38723927026554247076497794121196453103814197268488832650452990247100996042823
Line 180, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 525972859730 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 525972859730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---