AES/MASKED Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	130.339us	1	1	100.00
V1	smoke	aes_smoke	13.000s	1.018ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	84.442us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	92.431us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	457.659us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	709.757us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	285.764us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	92.431us	20	20	100.00
		aes_csr_aliasing	6.000s	709.757us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	1.018ms	50	50	100.00
		aes_config_error	33.000s	4.461ms	50	50	100.00
		aes_stress	1.033m	3.345ms	50	50	100.00
V2	key_length	aes_smoke	13.000s	1.018ms	50	50	100.00
		aes_config_error	33.000s	4.461ms	50	50	100.00
		aes_stress	1.033m	3.345ms	50	50	100.00
V2	back2back	aes_stress	1.033m	3.345ms	50	50	100.00
		aes_b2b	25.000s	418.707us	50	50	100.00
V2	backpressure	aes_stress	1.033m	3.345ms	50	50	100.00
V2	multi_message	aes_smoke	13.000s	1.018ms	50	50	100.00
		aes_config_error	33.000s	4.461ms	50	50	100.00
		aes_stress	1.033m	3.345ms	50	50	100.00
		aes_alert_reset	18.000s	1.263ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	7.000s	228.752us	50	50	100.00
		aes_config_error	33.000s	4.461ms	50	50	100.00
		aes_alert_reset	18.000s	1.263ms	50	50	100.00
V2	trigger_clear_test	aes_clear	22.000s	1.278ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	229.651us	1	1	100.00
V2	reset_recovery	aes_alert_reset	18.000s	1.263ms	50	50	100.00
V2	stress	aes_stress	1.033m	3.345ms	50	50	100.00
V2	sideload	aes_stress	1.033m	3.345ms	50	50	100.00
		aes_sideload	19.000s	1.039ms	50	50	100.00
V2	deinitialization	aes_deinit	25.000s	2.702ms	50	50	100.00
V2	stress_all	aes_stress_all	51.000s	4.632ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	80.232us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	180.616us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	180.616us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	84.442us	5	5	100.00
		aes_csr_rw	5.000s	92.431us	20	20	100.00
		aes_csr_aliasing	6.000s	709.757us	5	5	100.00
		aes_same_csr_outstanding	6.000s	596.105us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	84.442us	5	5	100.00
		aes_csr_rw	5.000s	92.431us	20	20	100.00
		aes_csr_aliasing	6.000s	709.757us	5	5	100.00
		aes_same_csr_outstanding	6.000s	596.105us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	36.000s	3.839ms	50	50	100.00
V2S	fault_inject	aes_fi	12.000s	2.049ms	49	50	98.00
		aes_control_fi	48.000s	10.003ms	275	300	91.67
		aes_cipher_fi	42.000s	10.017ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	121.367us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	121.367us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	121.367us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	121.367us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	103.140us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	1.589ms	5	5	100.00
		aes_tl_intg_err	7.000s	1.117ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	1.117ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	18.000s	1.263ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	121.367us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	1.018ms	50	50	100.00
		aes_stress	1.033m	3.345ms	50	50	100.00
		aes_alert_reset	18.000s	1.263ms	50	50	100.00
		aes_core_fi	21.000s	2.622ms	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	121.367us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	140.847us	50	50	100.00
		aes_stress	1.033m	3.345ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.033m	3.345ms	50	50	100.00
		aes_sideload	19.000s	1.039ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	140.847us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	140.847us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	140.847us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	140.847us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	140.847us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.033m	3.345ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.033m	3.345ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	12.000s	2.049ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	12.000s	2.049ms	49	50	98.00
		aes_control_fi	48.000s	10.003ms	275	300	91.67
		aes_cipher_fi	42.000s	10.017ms	337	350	96.29
		aes_ctr_fi	6.000s	157.996us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	12.000s	2.049ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	12.000s	2.049ms	49	50	98.00
		aes_control_fi	48.000s	10.003ms	275	300	91.67
		aes_cipher_fi	42.000s	10.017ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	42.000s	10.017ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	12.000s	2.049ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	12.000s	2.049ms	49	50	98.00
		aes_control_fi	48.000s	10.003ms	275	300	91.67
		aes_ctr_fi	6.000s	157.996us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	12.000s	2.049ms	49	50	98.00
		aes_control_fi	48.000s	10.003ms	275	300	91.67
		aes_cipher_fi	42.000s	10.017ms	337	350	96.29
		aes_ctr_fi	6.000s	157.996us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	18.000s	1.263ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	12.000s	2.049ms	49	50	98.00
		aes_control_fi	48.000s	10.003ms	275	300	91.67
		aes_cipher_fi	42.000s	10.017ms	337	350	96.29
		aes_ctr_fi	6.000s	157.996us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	12.000s	2.049ms	49	50	98.00
		aes_control_fi	48.000s	10.003ms	275	300	91.67
		aes_cipher_fi	42.000s	10.017ms	337	350	96.29
		aes_ctr_fi	6.000s	157.996us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	12.000s	2.049ms	49	50	98.00
		aes_control_fi	48.000s	10.003ms	275	300	91.67
		aes_ctr_fi	6.000s	157.996us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	12.000s	2.049ms	49	50	98.00
		aes_control_fi	48.000s	10.003ms	275	300	91.67
		aes_cipher_fi	42.000s	10.017ms	337	350	96.29
V2S		TOTAL			946	985	96.04
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	45.000s	3.855ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1553	1602	96.94

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.41	98.65	96.56	99.46	95.57	98.07	97.78	99.11	97.99

Failure Buckets

Job timed out after * minutes has 15 failures:
- Test aes_control_fi has 15 failures.
  - 17.aes_control_fi.75933144997538851434641061208175996130502542056850699730286445163445974619098
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 18.aes_control_fi.7273818418216215410115553516214064981503337886792733795832129437737790749388
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 4.aes_cipher_fi.93051239438181372594175842102977569930066406413752561350430421891677630965075
    Line 147, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011731497 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011731497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 20.aes_cipher_fi.78197374715768809015914866552258164652254116393519150498658076545540612187290
    Line 139, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10066735697 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10066735697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 6.aes_control_fi.46519890944142619152891672023467254308155306020582755959669685040621804004598
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005195997 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005195997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_control_fi.60779099218738130741057395781854546006652093094612845160705748468172981235692
    Line 142, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10025352037 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025352037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.113685333778182660768380043799262685762203420091503553257010483216226681286666
Line 405, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 652433578 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 652433578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.55226354424029902095423576500134049011060657340801628898277984673327268961184
Line 716, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2230398809 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2230398809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 4.aes_stress_all_with_rand_reset.21525160751578188891414550032259723887257831687877627839982315848914301760149
    Line 431, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 320976503 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 320976503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.114866295056262204101233460896294187382783619784056277764468252454310662465977
    Line 131, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  95898096 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  95898096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.86383477639298545560747254218912615239182764199048481901559568432040159305220
    Line 325, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2414518958 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2414518958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

4.aes_fi.76461455069145379426392088442196976273674177267948578404175849865111642862376
Line 554, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 16501878 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 16481045 PS)
  UVM_ERROR @  16501878 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  16501878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.25850642536826774303521581022895413118976877797197423698555191035806002057525
    Line 203, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 319790712 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 319790712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```