AES/UNMASKED Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	32.000s	65.058us	1	1	100.00
V1	smoke	aes_smoke	31.000s	59.026us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	54.192us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	91.585us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	1.367ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	2.172ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	92.567us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	91.585us	20	20	100.00
		aes_csr_aliasing	7.000s	2.172ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	31.000s	59.026us	50	50	100.00
		aes_config_error	30.000s	72.635us	50	50	100.00
		aes_stress	31.000s	73.530us	50	50	100.00
V2	key_length	aes_smoke	31.000s	59.026us	50	50	100.00
		aes_config_error	30.000s	72.635us	50	50	100.00
		aes_stress	31.000s	73.530us	50	50	100.00
V2	back2back	aes_stress	31.000s	73.530us	50	50	100.00
		aes_b2b	30.000s	72.257us	50	50	100.00
V2	backpressure	aes_stress	31.000s	73.530us	50	50	100.00
V2	multi_message	aes_smoke	31.000s	59.026us	50	50	100.00
		aes_config_error	30.000s	72.635us	50	50	100.00
		aes_stress	31.000s	73.530us	50	50	100.00
		aes_alert_reset	27.000s	84.504us	50	50	100.00
V2	failure_test	aes_man_cfg_err	31.000s	135.493us	50	50	100.00
		aes_config_error	30.000s	72.635us	50	50	100.00
		aes_alert_reset	27.000s	84.504us	50	50	100.00
V2	trigger_clear_test	aes_clear	28.000s	63.894us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	35.000s	309.744us	1	1	100.00
V2	reset_recovery	aes_alert_reset	27.000s	84.504us	50	50	100.00
V2	stress	aes_stress	31.000s	73.530us	50	50	100.00
V2	sideload	aes_stress	31.000s	73.530us	50	50	100.00
		aes_sideload	24.000s	207.227us	50	50	100.00
V2	deinitialization	aes_deinit	33.000s	87.973us	50	50	100.00
V2	stress_all	aes_stress_all	21.000s	790.854us	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	56.011us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	188.526us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	188.526us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	54.192us	5	5	100.00
		aes_csr_rw	5.000s	91.585us	20	20	100.00
		aes_csr_aliasing	7.000s	2.172ms	5	5	100.00
		aes_same_csr_outstanding	6.000s	269.909us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	54.192us	5	5	100.00
		aes_csr_rw	5.000s	91.585us	20	20	100.00
		aes_csr_aliasing	7.000s	2.172ms	5	5	100.00
		aes_same_csr_outstanding	6.000s	269.909us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	19.000s	91.428us	50	50	100.00
V2S	fault_inject	aes_fi	18.000s	90.193us	49	50	98.00
		aes_control_fi	34.000s	10.081ms	269	300	89.67
		aes_cipher_fi	34.000s	10.002ms	318	350	90.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	119.743us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	119.743us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	119.743us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	119.743us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	247.132us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	2.083ms	5	5	100.00
		aes_tl_intg_err	9.000s	2.175ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	2.175ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	27.000s	84.504us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	119.743us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	31.000s	59.026us	50	50	100.00
		aes_stress	31.000s	73.530us	50	50	100.00
		aes_alert_reset	27.000s	84.504us	50	50	100.00
		aes_core_fi	4.117m	10.010ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	119.743us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	31.000s	121.593us	50	50	100.00
		aes_stress	31.000s	73.530us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	31.000s	73.530us	50	50	100.00
		aes_sideload	24.000s	207.227us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	31.000s	121.593us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	31.000s	121.593us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	31.000s	121.593us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	31.000s	121.593us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	31.000s	121.593us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	31.000s	73.530us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	31.000s	73.530us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	18.000s	90.193us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	18.000s	90.193us	49	50	98.00
		aes_control_fi	34.000s	10.081ms	269	300	89.67
		aes_cipher_fi	34.000s	10.002ms	318	350	90.86
		aes_ctr_fi	12.000s	131.033us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	18.000s	90.193us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	18.000s	90.193us	49	50	98.00
		aes_control_fi	34.000s	10.081ms	269	300	89.67
		aes_cipher_fi	34.000s	10.002ms	318	350	90.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	34.000s	10.002ms	318	350	90.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	18.000s	90.193us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	18.000s	90.193us	49	50	98.00
		aes_control_fi	34.000s	10.081ms	269	300	89.67
		aes_ctr_fi	12.000s	131.033us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	18.000s	90.193us	49	50	98.00
		aes_control_fi	34.000s	10.081ms	269	300	89.67
		aes_cipher_fi	34.000s	10.002ms	318	350	90.86
		aes_ctr_fi	12.000s	131.033us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	27.000s	84.504us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	18.000s	90.193us	49	50	98.00
		aes_control_fi	34.000s	10.081ms	269	300	89.67
		aes_cipher_fi	34.000s	10.002ms	318	350	90.86
		aes_ctr_fi	12.000s	131.033us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	18.000s	90.193us	49	50	98.00
		aes_control_fi	34.000s	10.081ms	269	300	89.67
		aes_cipher_fi	34.000s	10.002ms	318	350	90.86
		aes_ctr_fi	12.000s	131.033us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	18.000s	90.193us	49	50	98.00
		aes_control_fi	34.000s	10.081ms	269	300	89.67
		aes_ctr_fi	12.000s	131.033us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	18.000s	90.193us	49	50	98.00
		aes_control_fi	34.000s	10.081ms	269	300	89.67
		aes_cipher_fi	34.000s	10.002ms	318	350	90.86
V2S		TOTAL			918	985	93.20
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	38.000s	6.404ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1525	1602	95.19

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.23	97.62	94.63	98.78	93.22	97.99	91.11	98.85	98.19

Failure Buckets

Job timed out after * minutes has 38 failures:
- Test aes_control_fi has 20 failures.
  - 4.aes_control_fi.109511954155678259274135266327037029444241921984177255497541988414371134206134
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 11.aes_control_fi.51949037153075411427795055401895848232429533630861766467282459938579145791341
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 18 more failures.
- Test aes_cipher_fi has 17 failures.
  - 15.aes_cipher_fi.15832522123731717443629433060922959998235861506350699394610989226308087616339
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 16.aes_cipher_fi.66823709047791189416968439587716404740291125315838317169025569405848718343254
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 15 more failures.
- Test aes_ctr_fi has 1 failures.
  - 21.aes_ctr_fi.19813976820572604423983687453794896886196957693123001068855428279504542782978
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/21.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_cipher_fi has 15 failures.
  - 4.aes_cipher_fi.43446851650091706651083103254533025436783619093192894555061299938673046043055
    Line 143, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011712382 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011712382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.aes_cipher_fi.76732252547114836345508998039997480142724673088996860175746899067316028947493
    Line 132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002452942 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002452942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 2.aes_control_fi.82013110861163474148788085403929146154351709209691115207167469063658489533766
    Line 132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004942033 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004942033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.aes_control_fi.58238701040453792740444394213722456725230162249123659801082891151062251578333
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009535466 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009535466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

3.aes_stress_all_with_rand_reset.59130655409972180308999769930923429182173630906105016174343169172486509222199
Line 610, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 831690407 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 831690407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.91369817185800286236071441735404657998292139138116967788866085945529026599300
Line 160, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  52318613 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  52318613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 0.aes_stress_all_with_rand_reset.43759865133118978404440078526336005252792968828438055992882366274493528164805
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  20900000 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  20900000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.aes_stress_all_with_rand_reset.38960532336222263020729809151768348065232311862539128552581954303141631554671
    Line 262, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 543394490 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 543394490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 2 failures:

Test aes_stress_all_with_rand_reset has 1 failures.

1.aes_stress_all_with_rand_reset.34259625469447557138949602093909538325263573106194012345159760885452458588772
Line 1053, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 2584573724 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 2584473724 PS)
  UVM_ERROR @ 2584573724 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 2584573724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 1 failures.

28.aes_fi.13537937816206169194791787930526148377095009652839756353186714107378373783304
Line 1690, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/28.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 5299736 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 5289319 PS)
  UVM_ERROR @   5299736 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   5299736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 7.aes_stress_all_with_rand_reset.42922706404168198978094044258110539694376326470970401400572018465043890332159
    Line 226, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 155027190 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 155027190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.2852731053192013502193975821194481871438132162826144108499266729008846943759
    Line 444, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 422108073 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 422108073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 7.aes_core_fi.72411960330945231810980072321165971776684775478245832484544223408542593508001
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009504459 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xca615184, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10009504459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 12.aes_core_fi.57646170544190036506536428753898840788355132977097419446509122230674348016450
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003513768 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003513768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```