CSRNG Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	270.125us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	185.212us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	44.882us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	38.000s	2.163ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	257.652us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	205.315us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	44.882us	20	20	100.00
		csrng_csr_aliasing	9.000s	257.652us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	23.000s	1.486ms	174	200	87.00
V2	alerts	csrng_alert	1.350m	6.499ms	500	500	100.00
V2	err	csrng_err	11.000s	31.011us	455	500	91.00
V2	cmds	csrng_cmds	6.850m	19.200ms	50	50	100.00
V2	life cycle	csrng_cmds	6.850m	19.200ms	50	50	100.00
V2	stress_all	csrng_stress_all	28.250m	142.996ms	49	50	98.00
V2	intr_test	csrng_intr_test	6.000s	57.325us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	66.524us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	20.000s	1.509ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	20.000s	1.509ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	185.212us	5	5	100.00
		csrng_csr_rw	6.000s	44.882us	20	20	100.00
		csrng_csr_aliasing	9.000s	257.652us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	246.243us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	185.212us	5	5	100.00
		csrng_csr_rw	6.000s	44.882us	20	20	100.00
		csrng_csr_aliasing	9.000s	257.652us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	246.243us	20	20	100.00
V2		TOTAL			1368	1440	95.00
V2S	tl_intg_err	csrng_sec_cm	11.000s	203.987us	5	5	100.00
		csrng_tl_intg_err	13.000s	554.776us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	131.522us	50	50	100.00
		csrng_csr_rw	6.000s	44.882us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.350m	6.499ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	28.250m	142.996ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
		csrng_sec_cm	11.000s	203.987us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
		csrng_sec_cm	11.000s	203.987us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
		csrng_sec_cm	11.000s	203.987us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
		csrng_sec_cm	11.000s	203.987us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
		csrng_sec_cm	11.000s	203.987us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
		csrng_sec_cm	11.000s	203.987us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
		csrng_sec_cm	11.000s	203.987us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.350m	6.499ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	28.250m	142.996ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.350m	6.499ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	554.776us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
		csrng_sec_cm	11.000s	203.987us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
		csrng_sec_cm	11.000s	203.987us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	23.000s	1.486ms	174	200	87.00
		csrng_err	11.000s	31.011us	455	500	91.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.833m	8.635ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1548	1630	94.97

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.59	98.53	96.44	99.86	97.42	92.08	88.00	96.13	89.94

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_cipher_control_fsm.sv,452): Assertion u_state_regs_A has failed has 42 failures:

Test csrng_intr has 13 failures.

12.csrng_intr.7703677751361432250399420426414477759205608101695446075466998898449384082274
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/12.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 95781591 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[0].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @  95781591 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  95781591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.csrng_intr.4681295943411093691879957687996927141915191140636986882837468475529660325852
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/37.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 51467939 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[1].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @  51467939 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  51467939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

Test csrng_err has 29 failures.

49.csrng_err.39026112130594799029452693882592319009299545890523219553986962549529877087074
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/49.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 3409485 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[1].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @   3409485 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   3409485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

72.csrng_err.45835911241994574939027035968477158707150901312589310473228921532340054465503
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/72.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 7888235 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[2].gen_fsm_n.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @   7888235 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   7888235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 27 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test csrng_stress_all_with_rand_reset has 10 failures.
  - 0.csrng_stress_all_with_rand_reset.115331790621807690771191736306780513660387050024003543494066218284163995599907
    Line 104, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8634638495 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8634638495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.csrng_stress_all_with_rand_reset.22844853324715711711732137895411232597476234365940181946505957768366057599929
    Line 115, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4891367969 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4891367969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_upd.sv,188): Assertion u_blk_enc_state_regs_A has failed has 8 failures:

Test csrng_intr has 2 failures.

62.csrng_intr.82936291106038946530632652515699484491328183912677173078773271150122759336265
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/62.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 59313413 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @  59313413 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @  59313413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

151.csrng_intr.115283000102582518773469999467311956108111044893869032130623582870741661489424
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/151.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 51164591 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @  51164591 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @  51164591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test csrng_err has 6 failures.

113.csrng_err.38063152545120870866985715495030315430556699007575517342224261353984744524961
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/113.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 2651772 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @   2651772 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @   2651772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

130.csrng_err.45823763862170950822889320973928024691590825293544432322367536133800529207401
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/130.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 8811475 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @   8811475 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @   8811475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_gen.sv,222): Assertion u_state_regs_A has failed has 6 failures:

Test csrng_intr has 4 failures.

29.csrng_intr.103509935642736141585649989197329596158094686973038440422156667787595164830515
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/29.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 817030601 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @ 817030601 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 817030601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.csrng_intr.33238822658734682213709287464541637047336887851693993762178794362831398242187
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/47.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 65216213 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @  65216213 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  65216213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test csrng_err has 2 failures.

90.csrng_err.51482685049620394878766987282384071771889473281546139697487435129527970285061
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/90.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 3179080 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @   3179080 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   3179080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

337.csrng_err.38613961121238795422473570480855284086501977471728805820943633153752192389948
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/337.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 1816879 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @   1816879 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   1816879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_upd.sv,222): Assertion u_outblk_state_regs_A has failed has 6 failures:

Test csrng_intr has 1 failures.

36.csrng_intr.33865357109690932713682659818479669945583552947192757140134545665389433642862
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/36.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 40068415 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @  40068415 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @  40068415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test csrng_err has 5 failures.

83.csrng_err.37523240359672981535797014467887863876080668745158710350849865356933267075901
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/83.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 10316090 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @  10316090 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @  10316090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

118.csrng_err.46338365520527242448477517120614217171368672801078926311101054901084603852621
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/118.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 11717736 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @  11717736 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @  11717736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_main_sm.sv,35): Assertion u_state_regs_A has failed has 6 failures:

Test csrng_err has 3 failures.

143.csrng_err.80329270217519506030268504657290366964965211875420513653435456349223112219716
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/143.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 1903635 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @   1903635 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   1903635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

373.csrng_err.78032424427199009137271254867396885115455425227453210152732824645746257834690
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/373.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 15925002 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @  15925002 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  15925002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test csrng_intr has 3 failures.

167.csrng_intr.56122755717081651576237314578758351563535668345840463220508118011795958547662
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/167.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 385311780 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @ 385311780 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 385311780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

169.csrng_intr.23367480611957784590216958211431122731206942506279253362852670946974758958554
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/169.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 307431197 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @ 307431197 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 307431197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,260): Assertion u_state_regs_A has failed has 3 failures:

Test csrng_intr has 3 failures.

70.csrng_intr.26014495349480168646534581534465125504303532826063749148498956589904546469020
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/70.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,260): (time 255012900 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.u_state_regs_A has failed
  UVM_ERROR @ 255012900 ps: (csrng_cmd_stage.sv:260) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 255012900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

89.csrng_intr.45437464072369068749254174299189633935173253238037832193648349892721649767848
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/89.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,260): (time 25099617 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.u_state_regs_A has failed
  UVM_ERROR @  25099617 ps: (csrng_cmd_stage.sv:260) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  25099617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 36.csrng_stress_all.29165196399346372594745634692523671566750154456858586223885440839756786789543
    Line 148, in log /nightly/runs/scratch/master/csrng-sim-xcelium/36.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 4420407552 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 4420407552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```