EDN Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 3.730s 49.226us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.550s 23.209us 5 5 100.00
V1 csr_rw edn_csr_rw 2.470s 29.767us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.990s 135.534us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.800s 250.698us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 3.600s 97.229us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.470s 29.767us 20 20 100.00
edn_csr_aliasing 2.800s 250.698us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.506m 8.753ms 300 300 100.00
V2 csrng_commands edn_genbits 1.506m 8.753ms 300 300 100.00
V2 genbits edn_genbits 1.506m 8.753ms 300 300 100.00
V2 interrupts edn_intr 3.760s 58.269us 50 50 100.00
V2 alerts edn_alert 4.030s 27.454us 200 200 100.00
V2 errs edn_err 3.850s 50.609us 100 100 100.00
V2 disable edn_disable 3.570s 42.279us 50 50 100.00
edn_disable_auto_req_mode 3.840s 42.913us 50 50 100.00
V2 stress_all edn_stress_all 9.260s 368.490us 50 50 100.00
V2 intr_test edn_intr_test 2.680s 127.310us 50 50 100.00
V2 alert_test edn_alert_test 3.720s 65.844us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.950s 1.415ms 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.950s 1.415ms 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.550s 23.209us 5 5 100.00
edn_csr_rw 2.470s 29.767us 20 20 100.00
edn_csr_aliasing 2.800s 250.698us 5 5 100.00
edn_same_csr_outstanding 2.860s 136.076us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.550s 23.209us 5 5 100.00
edn_csr_rw 2.470s 29.767us 20 20 100.00
edn_csr_aliasing 2.800s 250.698us 5 5 100.00
edn_same_csr_outstanding 2.860s 136.076us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.960s 1.999ms 5 5 100.00
edn_tl_intg_err 5.980s 308.803us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 3.790s 50.001us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 4.030s 27.454us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.960s 1.999ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.960s 1.999ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.960s 1.999ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.960s 1.999ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 4.030s 27.454us 200 200 100.00
edn_sec_cm 9.960s 1.999ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 4.030s 27.454us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 5.980s 308.803us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.645m 108.415ms 39 50 78.00
V3 TOTAL 39 50 78.00
TOTAL 1119 1130 99.03

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.04 98.87 94.29 97.02 93.02 96.33 99.78 92.94

Failure Buckets