ENTROPY_SRC/RNG_4BITS Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 9.000s 32.003us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 45.906us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 5.000s 76.500us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 12.000s 2.218ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 10.000s 214.573us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 168.929us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 5.000s 76.500us 20 20 100.00
entropy_src_csr_aliasing 10.000s 214.573us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 9.000s 32.003us 50 50 100.00
entropy_src_rng 5.500m 16.015ms 22 300 7.33
entropy_src_fw_ov 8.917m 20.077ms 167 300 55.67
V2 firmware_mode entropy_src_fw_ov 8.917m 20.077ms 167 300 55.67
V2 rng_mode entropy_src_rng 5.500m 16.015ms 22 300 7.33
V2 rng_max_rate entropy_src_rng_max_rate 7.717m 11.940ms 14 400 3.50
V2 health_checks entropy_src_rng 5.500m 16.015ms 22 300 7.33
V2 conditioning entropy_src_rng 5.500m 16.015ms 22 300 7.33
V2 interrupts entropy_src_rng 5.500m 16.015ms 22 300 7.33
entropy_src_intr 18.000s 2.743ms 50 50 100.00
V2 alerts entropy_src_rng 5.500m 16.015ms 22 300 7.33
entropy_src_functional_alerts 7.000s 62.901us 50 50 100.00
V2 stress_all entropy_src_stress_all 6.367m 20.173ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 8.633m 10.011ms 972 1000 97.20
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 34.000s 1.666ms 49 50 98.00
V2 intr_test entropy_src_intr_test 5.000s 59.365us 50 50 100.00
V2 alert_test entropy_src_alert_test 6.000s 47.395us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 1.097ms 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 1.097ms 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 45.906us 5 5 100.00
entropy_src_csr_rw 5.000s 76.500us 20 20 100.00
entropy_src_csr_aliasing 10.000s 214.573us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 132.196us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 45.906us 5 5 100.00
entropy_src_csr_rw 5.000s 76.500us 20 20 100.00
entropy_src_csr_aliasing 10.000s 214.573us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 132.196us 20 20 100.00
V2 TOTAL 1514 2340 64.70
V2S tl_intg_err entropy_src_sec_cm 6.000s 331.886us 5 5 100.00
entropy_src_tl_intg_err 7.000s 334.832us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.500m 16.015ms 22 300 7.33
entropy_src_cfg_regwen 6.000s 22.010us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.500m 16.015ms 22 300 7.33
V2S sec_cm_config_redun entropy_src_rng 5.500m 16.015ms 22 300 7.33
V2S sec_cm_intersig_mubi entropy_src_rng 5.500m 16.015ms 22 300 7.33
entropy_src_fw_ov 8.917m 20.077ms 167 300 55.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 8.633m 10.011ms 972 1000 97.20
entropy_src_sec_cm 6.000s 331.886us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 8.633m 10.011ms 972 1000 97.20
entropy_src_sec_cm 6.000s 331.886us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.500m 16.015ms 22 300 7.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 8.633m 10.011ms 972 1000 97.20
entropy_src_sec_cm 6.000s 331.886us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 8.633m 10.011ms 972 1000 97.20
entropy_src_sec_cm 6.000s 331.886us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 8.633m 10.011ms 972 1000 97.20
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 62.901us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 334.832us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 3.617m 8.017ms 6 50 12.00
V3 TOTAL 6 50 12.00
TOTAL 1700 2570 66.15

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
93.25 98.10 95.16 98.33 95.52 78.42 96.88 91.04 86.53

Failure Buckets