HMAC Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.910s	4.027ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.440s	26.551us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.430s	94.987us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.550s	22.601ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.130s	658.887us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	23.927m	284.527ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.430s	94.987us	20	20	100.00
		hmac_csr_aliasing	9.130s	658.887us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.638m	29.667ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.506m	3.149ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	5.146m	26.372ms	30	30	100.00
		hmac_test_sha384_vectors	9.332m	34.733ms	75	75	100.00
		hmac_test_sha512_vectors	10.624m	13.878ms	75	75	100.00
		hmac_test_hmac256_vectors	16.320s	1.280ms	50	50	100.00
		hmac_test_hmac384_vectors	18.030s	353.085us	60	60	100.00
		hmac_test_hmac512_vectors	20.720s	512.860us	75	75	100.00
V2	burst_wr	hmac_burst_wr	51.080s	19.135ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	24.356m	8.412ms	10	10	100.00
V2	error	hmac_error	2.106m	6.667ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.933m	2.355ms	10	10	100.00
V2	save_and_restore	hmac_smoke	16.910s	4.027ms	10	10	100.00
		hmac_long_msg	1.638m	29.667ms	10	10	100.00
		hmac_back_pressure	1.506m	3.149ms	25	25	100.00
		hmac_datapath_stress	24.356m	8.412ms	10	10	100.00
		hmac_burst_wr	51.080s	19.135ms	50	50	100.00
		hmac_stress_all	40.924m	28.072ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.910s	4.027ms	10	10	100.00
		hmac_long_msg	1.638m	29.667ms	10	10	100.00
		hmac_back_pressure	1.506m	3.149ms	25	25	100.00
		hmac_datapath_stress	24.356m	8.412ms	10	10	100.00
		hmac_wipe_secret	1.933m	2.355ms	10	10	100.00
		hmac_test_sha256_vectors	5.146m	26.372ms	30	30	100.00
		hmac_test_sha384_vectors	9.332m	34.733ms	75	75	100.00
		hmac_test_sha512_vectors	10.624m	13.878ms	75	75	100.00
		hmac_test_hmac256_vectors	16.320s	1.280ms	50	50	100.00
		hmac_test_hmac384_vectors	18.030s	353.085us	60	60	100.00
		hmac_test_hmac512_vectors	20.720s	512.860us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.910s	4.027ms	10	10	100.00
		hmac_long_msg	1.638m	29.667ms	10	10	100.00
		hmac_back_pressure	1.506m	3.149ms	25	25	100.00
		hmac_datapath_stress	24.356m	8.412ms	10	10	100.00
		hmac_burst_wr	51.080s	19.135ms	50	50	100.00
		hmac_error	2.106m	6.667ms	10	10	100.00
		hmac_wipe_secret	1.933m	2.355ms	10	10	100.00
		hmac_test_sha256_vectors	5.146m	26.372ms	30	30	100.00
		hmac_test_sha384_vectors	9.332m	34.733ms	75	75	100.00
		hmac_test_sha512_vectors	10.624m	13.878ms	75	75	100.00
		hmac_test_hmac256_vectors	16.320s	1.280ms	50	50	100.00
		hmac_test_hmac384_vectors	18.030s	353.085us	60	60	100.00
		hmac_test_hmac512_vectors	20.720s	512.860us	75	75	100.00
		hmac_stress_all	40.924m	28.072ms	50	50	100.00
V2	stress_all	hmac_stress_all	40.924m	28.072ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.100s	11.164us	50	50	100.00
V2	intr_test	hmac_intr_test	2.330s	109.245us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.300s	879.349us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.300s	879.349us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.440s	26.551us	5	5	100.00
		hmac_csr_rw	2.430s	94.987us	20	20	100.00
		hmac_csr_aliasing	9.130s	658.887us	5	5	100.00
		hmac_same_csr_outstanding	4.010s	229.029us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.440s	26.551us	5	5	100.00
		hmac_csr_rw	2.430s	94.987us	20	20	100.00
		hmac_csr_aliasing	9.130s	658.887us	5	5	100.00
		hmac_same_csr_outstanding	4.010s	229.029us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.350s	40.068us	5	5	100.00
		hmac_tl_intg_err	5.140s	3.067ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.140s	3.067ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.910s	4.027ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	9.460s	142.048us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	7.196m	21.276ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.260s	135.754us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.65	100.00	97.20	100.00	97.06	100.00	100.00	47.30