I2C Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.183m	7.575ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	35.750s	1.106ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.390s	76.906us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.330s	42.310us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.610s	459.198us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.690s	143.663us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.520s	400.492us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.330s	42.310us	20	20	100.00
		i2c_csr_aliasing	2.690s	143.663us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	12.170s	1.285ms	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	28.769m	73.013ms	25	50	50.00
V2	host_maxperf	i2c_host_perf	58.146m	73.606ms	50	50	100.00
V2	host_override	i2c_host_override	2.270s	30.212us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.181m	21.829ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.500m	2.582ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.800s	158.498us	50	50	100.00
		i2c_host_fifo_fmt_empty	21.710s	1.525ms	50	50	100.00
		i2c_host_fifo_reset_rx	12.300s	224.310us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.172m	4.488ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	35.320s	1.709ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	8.100s	676.122us	19	50	38.00
V2	target_glitch	i2c_target_glitch	13.660s	9.217ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	12.490m	47.862ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	8.940s	805.073us	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.155m	9.826ms	50	50	100.00
		i2c_target_intr_smoke	11.240s	2.788ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.620s	306.192us	50	50	100.00
		i2c_target_fifo_reset_tx	3.750s	285.623us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	17.652m	64.722ms	50	50	100.00
		i2c_target_stress_rd	1.155m	9.826ms	50	50	100.00
		i2c_target_intr_stress_wr	5.605m	23.284ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	12.660s	4.337ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	1.357m	4.753ms	43	50	86.00
V2	bad_address	i2c_target_bad_addr	9.980s	1.453ms	49	50	98.00
V2	target_mode_glitch	i2c_target_hrst	31.700s	10.050ms	28	50	56.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.130s	1.967ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.240s	262.424us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	58.146m	73.606ms	50	50	100.00
		i2c_host_perf_precise	24.111m	24.391ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	35.320s	1.709ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	30.060s	1.863ms	47	50	94.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.390s	554.947us	50	50	100.00
		i2c_target_nack_acqfull_addr	5.040s	483.378us	50	50	100.00
		i2c_target_nack_txstretch	3.400s	744.721us	34	50	68.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	20.930s	1.063ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.670s	1.090ms	50	50	100.00
V2	alert_test	i2c_alert_test	2.220s	22.148us	50	50	100.00
V2	intr_test	i2c_intr_test	2.270s	19.735us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	4.260s	146.604us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	4.260s	146.604us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.390s	76.906us	5	5	100.00
		i2c_csr_rw	2.330s	42.310us	20	20	100.00
		i2c_csr_aliasing	2.690s	143.663us	5	5	100.00
		i2c_same_csr_outstanding	2.630s	68.988us	18	20	90.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.390s	76.906us	5	5	100.00
		i2c_csr_rw	2.330s	42.310us	20	20	100.00
		i2c_csr_aliasing	2.690s	143.663us	5	5	100.00
		i2c_same_csr_outstanding	2.630s	68.988us	18	20	90.00
V2		TOTAL			1685	1792	94.03
V2S	tl_intg_err	i2c_tl_intg_err	3.820s	143.774us	20	20	100.00
		i2c_sec_cm	2.400s	243.290us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.820s	143.774us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	29.680s	1.049ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	4.040s	308.113us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	29.480s	8.681ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1865	2042	91.33

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.86	97.40	89.52	74.17	71.43	94.04	98.52	89.96

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 41 failures:

Test i2c_host_stress_all has 20 failures.

1.i2c_host_stress_all.73805113700867690741151169804325270178918890338804916958800677770652446066528
Line 123, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 58636627662 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @5540920

4.i2c_host_stress_all.71985315869409734802038883366288073409140448221382390163225079631318206492312
Line 256, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 22860966645 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4962342

... and 18 more failures.

Test i2c_host_mode_toggle has 21 failures.

1.i2c_host_mode_toggle.16959038335142968706463750236132475915448620735098069985071616459978784961368
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 336700523 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @13039

10.i2c_host_mode_toggle.96750867392246370750884393030699677042389094196657114090591767912937428897041
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 766513425 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @37837

... and 19 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 29 failures:
- Test i2c_target_unexp_stop has 28 failures.
  - 0.i2c_target_unexp_stop.83463353061175785665068588165267809162979921863423100152572253940402486712168
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 286833902 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 153 [0x99])
  UVM_INFO @ 286833902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_unexp_stop.94418649510641052086553542674450175618891803486852348223387617629355312332124
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  75276847 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 247 [0xf7])
  UVM_INFO @  75276847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 26 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 1.i2c_target_stress_all_with_rand_reset.44601888210135237837460107584152134667431432809269116814691272495358660816465
    Line 157, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8680579530 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 30 [0x1e])
  UVM_INFO @ 8680579530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 22 failures:
- Test i2c_target_hrst has 22 failures.
  - 2.i2c_target_hrst.24400026811050200381584816841813694242930295473395269696434266022942304940404
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10570593798 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10570593798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_hrst.87001617421916684361071971558617557100806504869834278740953073922308165489534
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10501628243 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10501628243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 20 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

Test i2c_host_stress_all_with_rand_reset has 9 failures.

0.i2c_host_stress_all_with_rand_reset.11866283252536807601506882441855289346797823841046004691696382247035616833325
Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 751780698 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 751780698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.111889556985494927369351297146610705822439518097295476335017131570773286965240
Line 99, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 129171316 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 129171316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test i2c_target_stress_all_with_rand_reset has 8 failures.

0.i2c_target_stress_all_with_rand_reset.71938895405017416085574114231014574665123615266248716271318790786948013381435
Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 137021122 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 137021122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.36376655538360114410224962685645165553215847722846385203651753528640707508830
Line 109, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 695762724 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 695762724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 17 failures:
- Test i2c_target_unexp_stop has 17 failures.
  - 6.i2c_target_unexp_stop.92655444578657820877414979266865575322348906705989135116440094844924937218222
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  33938219 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  33938219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.i2c_target_unexp_stop.31407777584975237210219813818706362801955035718760549367559810749643857989406
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1405283627 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1405283627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 16 failures:
- Test i2c_target_nack_txstretch has 16 failures.
  - 0.i2c_target_nack_txstretch.100581285263681912267021632379738133516681642269538553875340611325395157627001
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 779739161 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 779739161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_nack_txstretch.89702074937212371612733632804829095376880566567001726167693339237257065947012
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 724045901 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 724045901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 8 failures:

Test i2c_host_mode_toggle has 8 failures.

0.i2c_host_mode_toggle.30162578055196571471012887224359362102597841247468772340311942074949390151678
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 346107909 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

3.i2c_host_mode_toggle.17929314479934908376460566121070494979013933032930260414590466715620333803963
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 170994049 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 6 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 7 failures:
- Test i2c_target_stretch has 7 failures.
  - 11.i2c_target_stretch.53241988361396496899082980711989157878521386851301916526660379579871152607814
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10009712735 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10009712735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.i2c_target_stretch.41781053893442045072860842382449770059478706643760047196819685602029231719559
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10011078824 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10011078824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:

Test i2c_target_unexp_stop has 5 failures.

5.i2c_target_unexp_stop.66867476355873980207627478573164881639204465572601006990963612621490175050792
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @  88059412 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @  88059412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_target_unexp_stop.71353671558543018523681114547710664845226924813718470893295802590621811713124
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @  47861735 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @  47861735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test i2c_target_tx_stretch_ctrl has 3 failures.
  - 23.i2c_target_tx_stretch_ctrl.20250214614855909309329714277547517041546268494970047533992497828376461653438
    Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/23.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 40.i2c_target_tx_stretch_ctrl.68157004263233349388892638260327420043245261622957279269671843497490735848236
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/40.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:525) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
- Test i2c_same_csr_outstanding has 2 failures.
  - 6.i2c_same_csr_outstanding.42463307590302901516627315256099107886350968764892208340581287854894335807604
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  20351826 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  20351826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.i2c_same_csr_outstanding.71091229360623479607957991097199904744268859117010087847195184206351303354613
    Line 75, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 119229424 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @ 119229424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:

Test i2c_host_mode_toggle has 2 failures.

8.i2c_host_mode_toggle.89870872645432021670335647737767997334701529642205490179455181951705550240990
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log

  UVM_FATAL @ 192627794 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x60cecd14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 192627794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.i2c_host_mode_toggle.85491502173598519047168950436442200499017992948050764699453392903313029777961
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/34.i2c_host_mode_toggle/latest/run.log

  UVM_FATAL @ 104392181 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xb1138314, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 104392181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job timed out after * minutes has 2 failures:
- Test i2c_host_stress_all has 2 failures.
  - 15.i2c_host_stress_all.36440280468483690650575351822949276021189530099593868111491311341148097835718
    Log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 26.i2c_host_stress_all.60055919248321498186368319419060975018475634102245074086840516400145975112059
    Log /nightly/runs/scratch/master/i2c-sim-vcs/26.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 2 failures.

22.i2c_host_stress_all.39715806373028299868920880773340332054744477025716707479302288612264536460060
Line 267, in log /nightly/runs/scratch/master/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 7615418766 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @5902632

25.i2c_host_stress_all.61090409537561902191202298343371511845973009123745293997365369621604149294220
Line 200, in log /nightly/runs/scratch/master/i2c-sim-vcs/25.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 4727267336 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @976872

UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 3.i2c_host_stress_all_with_rand_reset.63666802387272700121080748311158995166138446306410686252988775818787009030894
    Line 95, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 153736869 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 153736869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 6.i2c_target_stress_all_with_rand_reset.78381562170031357138868123398799826978681828126590174131708637155754735837808
    Line 95, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 526183341 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 526183341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_target_bad_addr has 1 failures.
  - 15.i2c_target_bad_addr.58280869819942416983554747997739754016802803858813900835346224494285748267168
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 19.i2c_host_stress_all.33239220563638343128629936775961365616997021280942291234285628154859807718836
    Line 103, in log /nightly/runs/scratch/master/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 1707321035 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
```