KEYMGR Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	20.960s	4.704ms	50	50	100.00
V1	random	keymgr_random	1.223m	6.778ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.460s	30.287us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.560s	31.420us	15	20	75.00
V1	csr_bit_bash	keymgr_csr_bit_bash	19.740s	878.697us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.880s	1.448ms	3	5	60.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.590s	53.426us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.560s	31.420us	15	20	75.00
		keymgr_csr_aliasing	7.880s	1.448ms	3	5	60.00
V1		TOTAL			146	155	94.19
V2	cfgen_during_op	keymgr_cfg_regwen	1.502m	8.837ms	50	50	100.00
V2	sideload	keymgr_sideload	33.910s	1.310ms	50	50	100.00
		keymgr_sideload_kmac	35.520s	1.129ms	50	50	100.00
		keymgr_sideload_aes	33.130s	1.983ms	50	50	100.00
		keymgr_sideload_otbn	35.620s	3.009ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	24.870s	2.651ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	9.820s	340.157us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.720s	207.673us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	47.870s	2.203ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	51.570s	8.009ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	23.140s	2.047ms	50	50	100.00
V2	stress_all	keymgr_stress_all	7.121m	102.808ms	50	50	100.00
V2	intr_test	keymgr_intr_test	2.520s	13.384us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.540s	12.672us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.420s	132.385us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.420s	132.385us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.460s	30.287us	5	5	100.00
		keymgr_csr_rw	2.560s	31.420us	15	20	75.00
		keymgr_csr_aliasing	7.880s	1.448ms	3	5	60.00
		keymgr_same_csr_outstanding	4.630s	335.913us	17	20	85.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.460s	30.287us	5	5	100.00
		keymgr_csr_rw	2.560s	31.420us	15	20	75.00
		keymgr_csr_aliasing	7.880s	1.448ms	3	5	60.00
		keymgr_same_csr_outstanding	4.630s	335.913us	17	20	85.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	16.270s	5.690ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	16.270s	5.690ms	5	5	100.00
		keymgr_tl_intg_err	8.260s	255.331us	12	20	60.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.960s	313.149us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.960s	313.149us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.960s	313.149us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.960s	313.149us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	11.720s	524.898us	11	20	55.00
V2S	prim_count_check	keymgr_sec_cm	16.270s	5.690ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	16.270s	5.690ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.260s	255.331us	12	20	60.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.960s	313.149us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.502m	8.837ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.223m	6.778ms	50	50	100.00
		keymgr_csr_rw	2.560s	31.420us	15	20	75.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.223m	6.778ms	50	50	100.00
		keymgr_csr_rw	2.560s	31.420us	15	20	75.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.223m	6.778ms	50	50	100.00
		keymgr_csr_rw	2.560s	31.420us	15	20	75.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	9.820s	340.157us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	51.570s	8.009ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	51.570s	8.009ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.223m	6.778ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	14.760s	1.249ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	16.270s	5.690ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	16.270s	5.690ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	16.270s	5.690ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	18.370s	2.043ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	9.820s	340.157us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	16.270s	5.690ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	16.270s	5.690ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	16.270s	5.690ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	18.370s	2.043ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	18.370s	2.043ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	16.270s	5.690ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	18.370s	2.043ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	16.270s	5.690ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	18.370s	2.043ms	50	50	100.00
V2S		TOTAL			147	165	89.09
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	25.300s	2.422ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1062	1110	95.68

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.13	97.83	98.30	100.00	99.01	98.63	91.21

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 29 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 9 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.73390470765315326109879193113142122630706656069294108946388155751830721529622
Line 81, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @ 202704011 ps: (keymgr_csr_assert_fpv.sv:442) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @ 202704011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_shadow_reg_errors_with_csr_rw.26716746064444604219868765738036759009558468663949408081081230335223775356488
Line 81, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
  UVM_ERROR @  99216748 ps: (keymgr_csr_assert_fpv.sv:454) [ASSERT FAILED] attest_sw_binding_1_rd_A
  UVM_INFO @  99216748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test keymgr_same_csr_outstanding has 3 failures.

1.keymgr_same_csr_outstanding.111054507888007186252558215297726764829961182177890041108130277034128540113346
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
  UVM_ERROR @  51583743 ps: (keymgr_csr_assert_fpv.sv:490) [ASSERT FAILED] attest_sw_binding_7_rd_A
  UVM_INFO @  51583743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.keymgr_same_csr_outstanding.41467991923867558376152763579595571977110105190944334248757164755133274215674
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @  26795756 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @  26795756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_csr_rw has 5 failures.

2.keymgr_csr_rw.72225733173398666161587052656333516774321809669716430478917831319210625069588
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @   5243982 ps: (keymgr_csr_assert_fpv.sv:412) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @   5243982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.keymgr_csr_rw.69011557919786692352819556639688348632351388491176428632533561307672271539763
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/6.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @   8718168 ps: (keymgr_csr_assert_fpv.sv:478) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @   8718168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_csr_aliasing has 2 failures.

2.keymgr_csr_aliasing.80125371015206967380604496172498224939382104093544264583835667149819035303168
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
  UVM_ERROR @ 331605673 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_1_rd_A
  UVM_INFO @ 331605673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_csr_aliasing.10588662083518001853691756307124011193371722093691719131760733688077139662474
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @  70614544 ps: (keymgr_csr_assert_fpv.sv:418) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @  70614544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_mem_rw_with_rand_reset has 2 failures.

3.keymgr_csr_mem_rw_with_rand_reset.26881881126759361492885675840247058298323867752649254388771277814762832709835
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @  76633866 ps: (keymgr_csr_assert_fpv.sv:424) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @  76633866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.keymgr_csr_mem_rw_with_rand_reset.111983366330800544385982810277667478593677909651234686577430222850002090853888
Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @  31729748 ps: (keymgr_csr_assert_fpv.sv:484) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @  31729748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test keymgr_stress_all_with_rand_reset has 17 failures.
  - 2.keymgr_stress_all_with_rand_reset.89637643132205831640899955325917014701529742222508906688183537712146291627643
    Line 153, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 141119511 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 141119511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.keymgr_stress_all_with_rand_reset.46104074733314917779822908997786743650433059110747202546123723239392805993338
    Line 661, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1267080039 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1267080039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_sideload_protect has 1 failures.
  - 15.keymgr_sideload_protect.82655277837326790840887557149719976722885049935659270239689803093812301548033
    Line 163, in log /nightly/runs/scratch/master/keymgr-sim-vcs/15.keymgr_sideload_protect/latest/run.log
```
  UVM_ERROR @  11980547 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  11980547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 43.keymgr_lc_disable.108271624241991818824673687549167327217673706567048952815866095202529863486297
    Line 223, in log /nightly/runs/scratch/master/keymgr-sim-vcs/43.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  30877159 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
  UVM_INFO @  30877159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```