KMAC/MASKED Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.132m	12.551ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.700s	163.651us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.670s	110.358us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.540s	5.631ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.880s	148.555us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.560s	138.676us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.670s	110.358us	20	20	100.00
		kmac_csr_aliasing	6.880s	148.555us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.330s	21.053us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	3.140s	145.084us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.005h	387.611ms	50	50	100.00
V2	burst_write	kmac_burst_write	24.223m	68.507ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.677m	61.539ms	5	5	100.00
		kmac_test_vectors_sha3_256	26.374m	26.697ms	5	5	100.00
		kmac_test_vectors_sha3_384	26.423m	293.854ms	5	5	100.00
		kmac_test_vectors_sha3_512	20.316m	55.570ms	5	5	100.00
		kmac_test_vectors_shake_128	32.564m	21.114ms	5	5	100.00
		kmac_test_vectors_shake_256	33.457m	341.279ms	5	5	100.00
		kmac_test_vectors_kmac	4.510s	87.964us	5	5	100.00
		kmac_test_vectors_kmac_xof	5.000s	214.515us	5	5	100.00
V2	sideload	kmac_sideload	7.918m	67.731ms	50	50	100.00
V2	app	kmac_app	6.370m	25.441ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.684m	190.700ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.392m	8.365ms	50	50	100.00
V2	error	kmac_error	8.451m	86.795ms	50	50	100.00
V2	key_error	kmac_key_error	19.320s	1.992ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.420s	627.911us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.520s	826.623us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.130s	6.319ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.373m	22.602ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	32.480s	477.520us	50	50	100.00
V2	stress_all	kmac_stress_all	44.321m	78.301ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.410s	16.216us	50	50	100.00
V2	alert_test	kmac_alert_test	2.380s	15.322us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.410s	587.124us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.410s	587.124us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.700s	163.651us	5	5	100.00
		kmac_csr_rw	2.670s	110.358us	20	20	100.00
		kmac_csr_aliasing	6.880s	148.555us	5	5	100.00
		kmac_same_csr_outstanding	3.330s	1.008ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.700s	163.651us	5	5	100.00
		kmac_csr_rw	2.670s	110.358us	20	20	100.00
		kmac_csr_aliasing	6.880s	148.555us	5	5	100.00
		kmac_same_csr_outstanding	3.330s	1.008ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.130s	99.932us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.130s	99.932us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.130s	99.932us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.130s	99.932us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.010s	361.713us	15	20	75.00
V2S	tl_intg_err	kmac_sec_cm	1.764m	31.830ms	5	5	100.00
		kmac_tl_intg_err	4.930s	247.558us	17	20	85.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.930s	247.558us	17	20	85.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	32.480s	477.520us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.132m	12.551ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.918m	67.731ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.130s	99.932us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.764m	31.830ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.764m	31.830ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.764m	31.830ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.132m	12.551ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	32.480s	477.520us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.764m	31.830ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.816m	18.130ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.132m	12.551ms	50	50	100.00
V2S		TOTAL			67	75	89.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.660m	12.640ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			927	940	98.62

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.40	99.14	94.43	99.89	80.28	97.09	99.38	97.58

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 8 failures:

Test kmac_tl_intg_err has 3 failures.

0.kmac_tl_intg_err.16472119486297984519588491934732955951815050791600867333310957448026508433207
Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  37252325 ps: (kmac_csr_assert_fpv.sv:536) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  37252325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_tl_intg_err.55524172373564491680327730192893783178660941731310112936280669975017160895416
Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  22426248 ps: (kmac_csr_assert_fpv.sv:524) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  22426248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 5 failures.

1.kmac_shadow_reg_errors_with_csr_rw.43595104461363249802244485762592875549456796500749879457565471245129609459976
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @ 148526947 ps: (kmac_csr_assert_fpv.sv:494) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @ 148526947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.63051334196113821151596517791237503847393797821582269889307406872266647008203
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  27816984 ps: (kmac_csr_assert_fpv.sv:524) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  27816984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.12500606550877911928386353853761012409777024986571333345103429977298823805540
    Line 108, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 679472905 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 679472905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.113912179248815543634138332519989009797523469997801919719393584962455319246926
    Line 151, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4270553638 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 4270553638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.