KMAC/UNMASKED Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.133m	13.164ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.220s	52.896us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.510s	58.085us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.010s	2.589ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.020s	961.928us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.650s	390.877us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.510s	58.085us	20	20	100.00
		kmac_csr_aliasing	9.020s	961.928us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.050s	35.552us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.800s	18.947us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	47.253m	94.700ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.562m	38.749ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.153m	272.288ms	5	5	100.00
		kmac_test_vectors_sha3_256	29.961m	345.059ms	5	5	100.00
		kmac_test_vectors_sha3_384	23.265m	67.037ms	5	5	100.00
		kmac_test_vectors_sha3_512	12.238m	9.207ms	5	5	100.00
		kmac_test_vectors_shake_128	37.452m	377.293ms	5	5	100.00
		kmac_test_vectors_shake_256	30.428m	60.287ms	5	5	100.00
		kmac_test_vectors_kmac	4.060s	1.459ms	5	5	100.00
		kmac_test_vectors_kmac_xof	3.710s	50.159us	5	5	100.00
V2	sideload	kmac_sideload	7.129m	74.633ms	50	50	100.00
V2	app	kmac_app	6.077m	74.905ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.888m	184.952ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.731m	136.195ms	50	50	100.00
V2	error	kmac_error	7.103m	19.750ms	50	50	100.00
V2	key_error	kmac_key_error	15.550s	10.652ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.706m	10.083ms	39	50	78.00
V2	edn_timeout_error	kmac_edn_timeout_error	32.430s	452.031us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.630s	1.555ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.184m	12.697ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.400s	3.463ms	50	50	100.00
V2	stress_all	kmac_stress_all	41.018m	842.524ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.190s	62.128us	50	50	100.00
V2	alert_test	kmac_alert_test	2.310s	20.402us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.280s	184.385us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.280s	184.385us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.220s	52.896us	5	5	100.00
		kmac_csr_rw	2.510s	58.085us	20	20	100.00
		kmac_csr_aliasing	9.020s	961.928us	5	5	100.00
		kmac_same_csr_outstanding	3.750s	120.100us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.220s	52.896us	5	5	100.00
		kmac_csr_rw	2.510s	58.085us	20	20	100.00
		kmac_csr_aliasing	9.020s	961.928us	5	5	100.00
		kmac_same_csr_outstanding	3.750s	120.100us	20	20	100.00
V2		TOTAL			729	740	98.51
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.550s	1.141ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.550s	1.141ms	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.550s	1.141ms	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.550s	1.141ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.620s	724.703us	12	20	60.00
V2S	tl_intg_err	kmac_sec_cm	1.368m	20.533ms	5	5	100.00
		kmac_tl_intg_err	4.820s	243.375us	11	20	55.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.820s	243.375us	11	20	55.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.400s	3.463ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.133m	13.164ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.129m	74.633ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.550s	1.141ms	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.368m	20.533ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.368m	20.533ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.368m	20.533ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.133m	13.164ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.400s	3.463ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.368m	20.533ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.445m	37.960ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.133m	13.164ms	50	50	100.00
V2S		TOTAL			58	75	77.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.720m	26.331ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			905	940	96.28

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.82	97.23	94.38	100.00	73.55	95.98	99.35	96.27

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 15 failures:

Test kmac_tl_intg_err has 9 failures.

0.kmac_tl_intg_err.41403666018903293837251407291249966476321240830087131030789220509455495011573
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  78406110 ps: (kmac_csr_assert_fpv.sv:506) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  78406110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_tl_intg_err.88466964839611971649220199968033915554349877505874782441685479108688310731706
Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @   9468880 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @   9468880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 6 failures.

1.kmac_shadow_reg_errors_with_csr_rw.65602453826770939651057433238259617070046850146535903543055605001271596352017
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
  UVM_ERROR @   5842947 ps: (kmac_csr_assert_fpv.sv:518) [ASSERT FAILED] prefix_3_rd_A
  UVM_INFO @   5842947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors_with_csr_rw.689992654055618780900444727860270611560301850906440174198384954201291783292
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
  UVM_ERROR @  15267580 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_7_rd_A
  UVM_INFO @  15267580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.24113208312240299919268463219870262652243937916328667612675038750509268557162
    Line 102, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 256357642 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 256357642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.kmac_stress_all_with_rand_reset.71707554396546330870301841111484955107646254521329337430663546852142126842108
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 962203079 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 962203079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:

Test kmac_sideload_invalid has 2 failures.

16.kmac_sideload_invalid.34357850949040113764462843888304987971244099719367901462034002982423631761274
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/16.kmac_sideload_invalid/latest/run.log

  UVM_FATAL @ 10349415984 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe77d8000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10349415984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.kmac_sideload_invalid.85712342238474563688633460458246250058498521383359085565448492100054001548264
Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/24.kmac_sideload_invalid/latest/run.log

  UVM_FATAL @ 10082987694 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1ebc8000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10082987694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 2 failures:

Test kmac_sideload_invalid has 2 failures.

32.kmac_sideload_invalid.104384570059607741844592963970084433896308737782829187672491143658460559321571
Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log

  UVM_FATAL @ 10048854302 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa39ac000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10048854302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.kmac_sideload_invalid.75777725509641798358977638355500109573302249524608138053496417214293998556109
Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/40.kmac_sideload_invalid/latest/run.log

  UVM_FATAL @ 10039079827 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9c11a000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10039079827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 0.kmac_sideload_invalid.65711596609924591458393683875527528520078230089666228125398379861302639180403
    Line 91, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10587801600 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc1d4f000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
  UVM_INFO @ 10587801600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 2.kmac_stress_all_with_rand_reset.44899054237799983528184561043397891673439747552636141050082888227729468579896
    Line 209, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4843914543 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4843914543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 8.kmac_sideload_invalid.47435097298923779492589804735842198923762631112855581163406875026814651390233
    Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10020612830 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xab1f2000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10020612830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 8.kmac_shadow_reg_errors_with_csr_rw.5160501537546180780805075151029463198628767609579056742904578793879613001220
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  35726782 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2443283 [0x254813] vs 713398436 [0x2a8598a4]) Regname: kmac_reg_block.prefix_1.prefix_0 reset value: 0x0
  UVM_INFO @  35726782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 11.kmac_sideload_invalid.87383428560827560620943941703136734227351738940066824813804877703571716004963
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10146744067 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x60d10000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10146744067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 14.kmac_shadow_reg_errors_with_csr_rw.111227854311948004071758035826283269721070980213340916086360902201183211465729
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 101677700 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (747184236 [0x2c89206c] vs 0 [0x0]) Regname: kmac_reg_block.prefix_2 reset value: 0x0
  UVM_INFO @ 101677700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 27.kmac_sideload_invalid.83625766229985049026300455335002372844226786075601001296701269801741985385478
    Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/27.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10047349659 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x10e3d000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10047349659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 36.kmac_sideload_invalid.90475342146907244835914400413651473431118744553964510207719495878902198346965
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/36.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10085742287 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcdcb000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10085742287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 43.kmac_sideload_invalid.30220844857116532888552294337135851075086247282308184041477704043220474713945
    Line 95, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/43.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10585270533 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe2995000, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
  UVM_INFO @ 10585270533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 44.kmac_sideload_invalid.53774456368232056877625645642340667703090710303242556106405493314756883580781
    Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/44.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10187550100 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x25c9d000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
  UVM_INFO @ 10187550100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```