4a542c3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 13.000s | 144.045us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 56.000s | 189.739us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 10.000s | 28.122us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 9.000s | 15.705us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 28.047us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 9.000s | 19.617us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 12.000s | 32.766us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 9.000s | 15.705us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 9.000s | 19.617us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 51.000s | 366.081us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 50.000s | 1.453ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 38.000s | 251.198us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 1.417m | 223.677us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 6.300m | 16.062ms | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.317m | 339.754us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 19.000s | 51.488us | 60 | 60 | 100.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 12.000s | 24.415us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 44.000s | 143.262us | 9 | 10 | 90.00 |
| V2 | alert_test | otbn_alert_test | 8.000s | 42.393us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 38.000s | 36.660us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 41.000s | 98.424us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 41.000s | 98.424us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 10.000s | 28.122us | 5 | 5 | 100.00 |
| otbn_csr_rw | 9.000s | 15.705us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 9.000s | 19.617us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 12.000s | 26.551us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 10.000s | 28.122us | 5 | 5 | 100.00 |
| otbn_csr_rw | 9.000s | 15.705us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 9.000s | 19.617us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 12.000s | 26.551us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 245 | 246 | 99.59 | |||
| V2S | mem_integrity | otbn_imem_err | 17.000s | 52.055us | 10 | 10 | 100.00 |
| otbn_dmem_err | 17.000s | 43.285us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 16.778s | 4 | 5 | 80.00 | |
| otbn_controller_ispr_rdata_err | 15.962s | 4 | 5 | 80.00 | |||
| otbn_mac_bignum_acc_err | 16.000s | 56.829us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 11.000s | 21.079us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 17.000s | 48.025us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 10.000s | 42.571us | 2 | 2 | 100.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 9.000s | 19.080us | 10 | 10 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 |
| otbn_tl_intg_err | 1.167m | 576.274us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 59.000s | 100.702us | 18 | 20 | 90.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 |
| V2S | prim_count_check | otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 13.000s | 144.045us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 17.000s | 43.285us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 17.000s | 52.055us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 1.167m | 576.274us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 19.000s | 51.488us | 60 | 60 | 100.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 17.000s | 52.055us | 10 | 10 | 100.00 |
| otbn_dmem_err | 17.000s | 43.285us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 12.000s | 24.415us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 17.000s | 48.025us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 56.000s | 189.739us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 17.000s | 52.055us | 10 | 10 | 100.00 |
| otbn_dmem_err | 17.000s | 43.285us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 12.000s | 24.415us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 17.000s | 48.025us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 19.000s | 51.488us | 60 | 60 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 17.000s | 52.055us | 10 | 10 | 100.00 |
| otbn_dmem_err | 17.000s | 43.285us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 12.000s | 24.415us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 17.000s | 48.025us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 56.000s | 189.739us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 12.000s | 24.323us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 10.000s | 74.006us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.667m | 1.071ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.667m | 1.071ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 13.000s | 49.239us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 14.000s | 224.070us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 12.000s | 76.536us | 3 | 5 | 60.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 12.000s | 76.536us | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 11.000s | 16.711us | 5 | 7 | 71.43 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 56.000s | 189.739us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 56.000s | 189.739us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 56.000s | 189.739us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 6.300m | 16.062ms | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 56.000s | 189.739us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 56.000s | 189.739us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 26.000s | 67.874us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 56.000s | 189.739us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 6.367m | 2.407ms | 3 | 5 | 60.00 |
| V2S | TOTAL | 153 | 163 | 93.87 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 4.300m | 3.548ms | 4 | 10 | 40.00 |
| V3 | TOTAL | 4 | 10 | 40.00 | |||
| TOTAL | 568 | 585 | 97.09 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 99.04 | 99.64 | 96.00 | 99.72 | 93.17 | 93.41 | 97.44 | 91.19 | 100.00 |
Job returned non-zero exit code has 4 failures:
Test otbn_alu_bignum_mod_err has 1 failures.
0.otbn_alu_bignum_mod_err.16024115815847249860346315138854226969057288143904145906904810412461894744998
Log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest/run.log
make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 16024115815847249860346315138854226969057288143904145906904810412461894744998 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest run_opts='+en_cov=1 -covmodeldir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_alu_bignum_mod_err.1294547878 -covworkdir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_alu_bignum_mod_err.1294547878 -covoverwrite +otbn_elf_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=1294547878 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_alu_bignum_mod_err_vseq -nowarn DSEM2009' seed=16024115815847249860346315138854226969057288143904145906904810412461894744998 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_alu_bignum_mod_err_vseq
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 16024115815847249860346315138854226969057288143904145906904810412461894744998 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest
2025/06/22 13:41:01 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
Test otbn_controller_ispr_rdata_err has 1 failures.
0.otbn_controller_ispr_rdata_err.100852805746758621899848418184022986646249903858439749463649366540329817648506
Log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_controller_ispr_rdata_err/latest/run.log
make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 100852805746758621899848418184022986646249903858439749463649366540329817648506 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_controller_ispr_rdata_err/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_controller_ispr_rdata_err/latest run_opts='+en_cov=1 -covmodeldir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_controller_ispr_rdata_err.1334226298 -covworkdir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_controller_ispr_rdata_err.1334226298 -covoverwrite +otbn_elf_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_controller_ispr_rdata_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=1334226298 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_controller_ispr_rdata_err_vseq -nowarn DSEM2009' seed=100852805746758621899848418184022986646249903858439749463649366540329817648506 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_controller_ispr_rdata_err_vseq
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_controller_ispr_rdata_err/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_controller_ispr_rdata_err/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 100852805746758621899848418184022986646249903858439749463649366540329817648506 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_controller_ispr_rdata_err/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/0.otbn_controller_ispr_rdata_err/latest
2025/06/22 13:41:01 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
Test otbn_sw_errs_fatal_chk has 1 failures.
0.otbn_sw_errs_fatal_chk.2282149258901412767246819699056626737475459048405693075478535089031190767300
Log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/run.log
make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 2282149258901412767246819699056626737475459048405693075478535089031190767300 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest run_opts='+en_cov=1 -covmodeldir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_sw_errs_fatal_chk.770533060 -covworkdir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_sw_errs_fatal_chk.770533060 -covoverwrite +otbn_elf_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=770533060 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_sw_errs_fatal_chk_vseq -nowarn DSEM2009' seed=2282149258901412767246819699056626737475459048405693075478535089031190767300 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_sw_errs_fatal_chk_vseq
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 2282149258901412767246819699056626737475459048405693075478535089031190767300 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest
2025/06/22 13:41:03 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
Test otbn_stack_addr_integ_chk has 1 failures.
0.otbn_stack_addr_integ_chk.85383587430370882750137571180031856767630857411837016373338802418630839643286
Log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 85383587430370882750137571180031856767630857411837016373338802418630839643286 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest run_opts='+en_cov=1 -covmodeldir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_stack_addr_integ_chk.92417174 -covworkdir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_stack_addr_integ_chk.92417174 -covoverwrite +otbn_elf_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=92417174 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_stack_addr_integ_chk_vseq -nowarn DSEM2009' seed=85383587430370882750137571180031856767630857411837016373338802418630839643286 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_stack_addr_integ_chk_vseq
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 85383587430370882750137571180031856767630857411837016373338802418630839643286 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest
2025/06/22 13:41:08 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
3.otbn_stress_all_with_rand_reset.114908185291287847366182429966950872619840289224462260004365375421983445996504
Line 158, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 138699889 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 138699889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.otbn_stress_all_with_rand_reset.62795804763201337313499576361949740081720930662405087328102481806998705968428
Line 254, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1167704071 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1167704071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:
Test otbn_sec_wipe_err has 2 failures.
3.otbn_sec_wipe_err.38689923336814358417062056108695087927268341770032421447382523215956947488781
Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22737466 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 22737466 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 22737466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.otbn_sec_wipe_err.67870093156735513015870123633490686006839313388191815632748114639022832873254
Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 42230474 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 42230474 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 42230474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stack_addr_integ_chk has 1 failures.
4.otbn_stack_addr_integ_chk.103776736532439444087881181919607712811349742648055119928891436054593006747973
Line 105, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 20038634 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 20038634 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 20038634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 2 failures:
3.otbn_sec_cm.68045742189514730342422533296695558144180119621188235739645645100488085759504
Line 110, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 75074552 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 75074552 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_ERROR @ 75074552 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
UVM_INFO @ 75074552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.otbn_sec_cm.48321984459636793318564942152710982642203092209128557463866499259917956488544
Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 118364870 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 118364870 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_ERROR @ 118364870 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
UVM_INFO @ 118364870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
5.otbn_stress_all_with_rand_reset.24745084841458878104366769707846555419574648548928302887763449307084360483111
Line 163, in log /nightly/runs/scratch/master/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 443122667 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 443122667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.otbn_stress_all_with_rand_reset.39915022166671254205388680524235556961948978055796509041591168253933933229841
Line 164, in log /nightly/runs/scratch/master/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 445461657 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 445461657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
0.otbn_stress_all_with_rand_reset.87535289165001324477198139795133708346637444402173311613910119960204361322233
Line 250, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 973843450 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 973843450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:
5.otbn_passthru_mem_tl_intg_err.100460446782203689543891228802305172266066137681228152880069699940304379013765
Line 122, in log /nightly/runs/scratch/master/otbn-sim-xcelium/5.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 171522089 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 171522089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
7.otbn_passthru_mem_tl_intg_err.52042244169238347907188943026329693288337752386674105858435914753667632708920
Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/7.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 10248229 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 10248229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---