4a542c3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 37.000s | 561.931us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 5.000s | 34.739us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 5.000s | 16.297us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 7.000s | 1.338ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 4.000s | 14.776us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 5.000s | 205.870us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 5.000s | 16.297us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 4.000s | 14.776us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 51.750m | 600.000ms | 27 | 50 | 54.00 |
| V2 | cnt_rollover | cnt_rollover | 1.483m | 3.418ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 37.000s | 87.567us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.999h | 10.000s | 17 | 50 | 34.00 |
| V2 | alert_test | pattgen_alert_test | 37.000s | 19.381us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 5.000s | 37.978us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 6.000s | 151.277us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 6.000s | 151.277us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 5.000s | 34.739us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 16.297us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 4.000s | 14.776us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 88.467us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 5.000s | 34.739us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 16.297us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 4.000s | 14.776us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 88.467us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 284 | 340 | 83.53 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 6.000s | 441.704us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 37.000s | 75.490us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 6.000s | 441.704us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.067m | 18.620ms | 3 | 50 | 6.00 |
| V3 | TOTAL | 3 | 50 | 6.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.417m | 10.015ms | 30 | 50 | 60.00 | |
| TOTAL | 447 | 570 | 78.42 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.72 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 100.00 | 88.15 |
UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 45 failures:
0.pattgen_stress_all_with_rand_reset.97833484385603696527429295992886804588342596601813986040643068004703428416388
Line 466, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4033585050 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 4033593544 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4033593544 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 10/10
UVM_INFO @ 4033753544 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.10430469277455202444232189587481287976208687790783575273844173051953996260595
Line 259, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7817945155 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 7817961638 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7817961638 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/5
UVM_INFO @ 7818222506 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 43 more failures.
Job timed out after * minutes has 26 failures:
4.pattgen_perf.79176531537695584793934442224958112032483000611962864976019556651403513206733
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/4.pattgen_perf/latest/run.log
Job timed out after 60 minutes
8.pattgen_perf.62989090101332326159603215153055229285889688767800540160346244288538634824524
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/8.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 11 more failures.
10.pattgen_stress_all.96527852756019558919999194397511892862908600941503603251524091704383184502306
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/10.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
11.pattgen_stress_all.54884505729894590156158065777600547433098457807124740799353703976544830538627
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/11.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 11 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 18 failures:
2.pattgen_stress_all.52573470939651746048727173763704912943785114265762384200545819369162189350716
Line 142, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log
UVM_ERROR @ 288624253 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10394
5.pattgen_stress_all.113180197348374416585539050777956657783779422113247500442275756773581270086560
Line 144, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all/latest/run.log
UVM_ERROR @ 592285154 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10405
... and 16 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 12 failures:
10.pattgen_perf.115334609721472775014239793797064006420825176565482145356296304896999840327649
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/10.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.pattgen_perf.103174433543367523005292898315799417661019695516420582575336333939081628282506
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/11.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
26.pattgen_stress_all.29926961969652866216136960586795947437495999591128623487888964246611069640289
Line 117, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/26.pattgen_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.pattgen_stress_all.24426847440073353579164640089521014493319421383148271043740359720874627859097
Line 108, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/27.pattgen_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 5 failures:
2.pattgen_inactive_level.61795058565953231733845554556390793908506206272602674990335081483021778851143
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10007610602 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa22e02d0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10007610602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.pattgen_inactive_level.35816110466118592340403830564800433550060077803218407009853042652496907827692
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/8.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10003068805 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5f76fdd0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10003068805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 2 failures:
2.pattgen_stress_all_with_rand_reset.97338606458840399711611675894012659226246155899581399325681489864087082607425
Line 117, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 454543924 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
22.pattgen_stress_all_with_rand_reset.84595255297704832254106145045221824224929077380605855796584506667605941859460
Line 135, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 240072483 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 2 failures:
3.pattgen_inactive_level.93541018792717045610717768741498295215557102742098629712470055572953574679085
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10015122878 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xdc0ec610, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10015122878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.pattgen_inactive_level.82312501230791996144625011338270207131953780785968914406755348239388982259423
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10018265191 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2a2c63d0, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10018265191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
15.pattgen_inactive_level.52411209713159798244411542846950296598082430571214542424216190296166960382024
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10010320553 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xff209b10, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10010320553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.pattgen_inactive_level.79260148400879316111145497537996213833671109313654522950247717643051385896382
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/38.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10015218399 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa857fc90, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10015218399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
16.pattgen_inactive_level.97983393557548674016812441303272596514355401396890090958274278509827483027985
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10023216452 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe131e190, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10023216452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.pattgen_inactive_level.56897332203731223300180836228562536128803090676647475702433119390553473755059
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/21.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10033521217 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x89791090, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10033521217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 2 failures:
25.pattgen_inactive_level.18150537612831406234411880783618873278312807237821660247321554085961338352655
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10027491688 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x7675490, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 10027491688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.pattgen_inactive_level.80325170713725715839577349590819135149871946292411097286234815946934073730999
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/35.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10046658963 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2cbeb5d0, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 10046658963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 2 failures:
30.pattgen_inactive_level.92133853164527238402546931104147868474983899727878661702484202227720886384821
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10022279280 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xda2d7710, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10022279280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.pattgen_inactive_level.108617855161279721194106777603368548667002256409697041070415068359727925942344
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10196416924 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x63b87710, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10196416924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
4.pattgen_inactive_level.49225645854779391734397099776839844370814476959345026175318433589674825218421
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10057483957 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xa4346dd0, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 10057483957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
6.pattgen_inactive_level.49961980665320068649767463288019429532685258772970916055622711998228953372386
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10048737046 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xbcce3690, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10048737046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
12.pattgen_inactive_level.1202251835725528389838218225796617919426518223017100700252115016734754164060
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10071230791 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x440ebd90, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10071230791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
17.pattgen_inactive_level.10805745897839032549220457929071573339871339682796084094866547810922674421347
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/17.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10011949416 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa81f16d0, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10011949416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
46.pattgen_inactive_level.103156854363303665487527394658093986851255976825115772063244539013448355101556
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10031015522 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xa521efd0, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10031015522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---