ROM_CTRL/32KB Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.740s	133.294us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	10.330s	2.013ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	8.010s	1.197ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.120s	128.122us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	7.580s	168.600us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.340s	190.651us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	8.010s	1.197ms	20	20	100.00
		rom_ctrl_csr_aliasing	7.580s	168.600us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.450s	136.787us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.260s	537.820us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.210s	233.675us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	39.840s	2.090ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	10.580s	313.624us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.230s	163.897us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	11.020s	378.072us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	11.020s	378.072us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	10.330s	2.013ms	5	5	100.00
		rom_ctrl_csr_rw	8.010s	1.197ms	20	20	100.00
		rom_ctrl_csr_aliasing	7.580s	168.600us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.550s	550.401us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	10.330s	2.013ms	5	5	100.00
		rom_ctrl_csr_rw	8.010s	1.197ms	20	20	100.00
		rom_ctrl_csr_aliasing	7.580s	168.600us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.550s	550.401us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.038m	3.815ms	14	20	70.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	29.130s	842.761us	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.714m	727.702us	5	5	100.00
		rom_ctrl_tl_intg_err	53.080s	322.383us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.714m	727.702us	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.714m	727.702us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.038m	3.815ms	14	20	70.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.038m	3.815ms	14	20	70.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.038m	3.815ms	14	20	70.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.038m	3.815ms	14	20	70.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.038m	3.815ms	14	20	70.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.714m	727.702us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.714m	727.702us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.740s	133.294us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.740s	133.294us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.740s	133.294us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	53.080s	322.383us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.038m	3.815ms	14	20	70.00
		rom_ctrl_kmac_err_chk	10.580s	313.624us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.038m	3.815ms	14	20	70.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.038m	3.815ms	14	20	70.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.038m	3.815ms	14	20	70.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	29.130s	842.761us	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.714m	727.702us	5	5	100.00
V2S		TOTAL			59	65	90.77
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.936m	9.211ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			260	266	97.74

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.73	99.27	100.00	100.00	99.64	98.98	100.00

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 6 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 6 failures.

    • 1.rom_ctrl_corrupt_sig_fatal_chk.112395582657489374584330661905587097407166123489693531763926908163470974769879
      Line 100, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1267981735 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1267981735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.rom_ctrl_corrupt_sig_fatal_chk.111685007789918442479401668269822923103921755282942397798981364823355303281576
      Line 101, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 7959760251 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 7959760251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.