RV_TIMER Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.170s	212.534us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.040s	56.483us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.210s	14.385us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.300s	1.623ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.230s	23.601us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.810s	116.019us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.210s	14.385us	20	20	100.00
		rv_timer_csr_aliasing	2.230s	23.601us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	22.090s	10.012ms	20	20	100.00
V2	disabled	rv_timer_disabled	6.790s	2.197ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	9.568m	333.619ms	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	9.568m	333.619ms	10	10	100.00
V2	stress	rv_timer_stress_all	10.230s	13.225ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.140s	37.995us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.220s	14.826us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	4.290s	119.543us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	4.290s	119.543us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.040s	56.483us	5	5	100.00
		rv_timer_csr_rw	2.210s	14.385us	20	20	100.00
		rv_timer_csr_aliasing	2.230s	23.601us	5	5	100.00
		rv_timer_same_csr_outstanding	2.400s	109.509us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.040s	56.483us	5	5	100.00
		rv_timer_csr_rw	2.210s	14.385us	20	20	100.00
		rv_timer_csr_aliasing	2.230s	23.601us	5	5	100.00
		rv_timer_same_csr_outstanding	2.400s	109.509us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.480s	186.350us	5	5	100.00
		rv_timer_tl_intg_err	3.110s	356.086us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	3.110s	356.086us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	2.070s	21.529us	10	10	100.00
V3	max_value	rv_timer_max	2.070s	41.903us	10	10	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.374m	49.113ms	20	20	100.00
V3		TOTAL			40	40	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.44	100.00	100.00	78.66	--	100.00	100.00	100.00