SPI_DEVICE/1R1W Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	5.214m	42.291ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.910s	85.260us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.950s	352.189us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.810s	7.539ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.260s	2.210ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.970s	124.005us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.950s	352.189us	20	20	100.00
		spi_device_csr_aliasing	24.260s	2.210ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.280s	21.170us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.440s	96.081us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.350s	19.663us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.270s	956.557ns	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.960s	5.230us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	11.640s	1.104ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.640s	1.104ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	26.280s	16.243ms	50	50	100.00
		spi_device_tpm_sts_read	2.620s	90.754us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	59.840s	102.223ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	29.060s	114.827ms	50	50	100.00
		spi_device_flash_all	3.933m	31.937ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	26.860s	151.067ms	50	50	100.00
		spi_device_flash_all	3.933m	31.937ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	26.860s	151.067ms	50	50	100.00
		spi_device_flash_all	3.933m	31.937ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	3.933m	31.937ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	25.850s	3.674ms	50	50	100.00
		spi_device_flash_all	3.933m	31.937ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	25.850s	3.674ms	50	50	100.00
		spi_device_flash_all	3.933m	31.937ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	25.850s	3.674ms	50	50	100.00
		spi_device_flash_all	3.933m	31.937ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	25.850s	3.674ms	50	50	100.00
		spi_device_flash_all	3.933m	31.937ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	25.850s	3.674ms	50	50	100.00
		spi_device_flash_all	3.933m	31.937ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	37.850s	12.777ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.692m	29.307ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.692m	29.307ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.692m	29.307ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	52.610s	9.074ms	50	50	100.00
		spi_device_read_buffer_direct	14.990s	1.669ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.692m	29.307ms	50	50	100.00
		spi_device_flash_all	3.933m	31.937ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	3.933m	31.937ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	3.933m	31.937ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	18.240s	3.697ms	49	50	98.00
V2	write_enable_disable	spi_device_cfg_cmd	18.240s	3.697ms	49	50	98.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	5.214m	42.291ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.648m	115.468ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.491m	124.288ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.280s	46.154us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.370s	134.091us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.240s	366.236us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.240s	366.236us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.910s	85.260us	5	5	100.00
		spi_device_csr_rw	3.950s	352.189us	20	20	100.00
		spi_device_csr_aliasing	24.260s	2.210ms	5	5	100.00
		spi_device_same_csr_outstanding	5.390s	723.644us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.910s	85.260us	5	5	100.00
		spi_device_csr_rw	3.950s	352.189us	20	20	100.00
		spi_device_csr_aliasing	24.260s	2.210ms	5	5	100.00
		spi_device_same_csr_outstanding	5.390s	723.644us	20	20	100.00
V2		TOTAL			939	961	97.71
V2S	tl_intg_err	spi_device_sec_cm	2.810s	258.671us	5	5	100.00
		spi_device_tl_intg_err	21.590s	5.685ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.590s	5.685ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	23.952m	1.500s	49	50	98.00
		TOTAL			1128	1151	98.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.80	99.12	96.50	71.19	89.36	98.41	95.76	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.107646332522064781857318649099013173762593025431314963879197183386744886932385
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   7516098 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[102])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   7516098 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   7516098 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[998])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.90370319142415087982434052312099116326554178925612470601965791797802737084710
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1038583 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[40])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1038583 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1038583 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[936])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.79901773284757976674703637370621865490432466461559178580437497593562049338505
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @   2909790 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5fa0b5 [10111111010000010110101] vs 0x0 [0])
  UVM_ERROR @   3007790 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2d4e72 [1011010100111001110010] vs 0x0 [0])
  UVM_ERROR @   3015790 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdd0e9b [110111010000111010011011] vs 0x0 [0])
  UVM_ERROR @   3061790 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb8cc6c [101110001100110001101100] vs 0x0 [0])
  UVM_ERROR @   3155790 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x568836 [10101101000100000110110] vs 0x0 [0])

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 4.spi_device_flash_mode_ignore_cmds.74974678654118741496007341367661892222319909925314041697161266999673111538272
    Line 125, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:2236) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_cfg_cmd has 1 failures.

43.spi_device_cfg_cmd.40561804068997535411767664237530340347115184886610143260279324363475389197100
Line 77, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 723146811 ps: (spi_device_scoreboard.sv:2236) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x49622) != exp '{'{other_status:'h396b14, wel:'h1, busy:'h0}, '{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h3c3fdc, wel:'h0, busy:'h0}}
  UVM_ERROR @ 723263091 ps: (spi_device_scoreboard.sv:2236) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x49622) != exp '{'{other_status:'h396b14, wel:'h1, busy:'h0}, '{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h3c3fdc, wel:'h0, busy:'h0}}
  UVM_ERROR @ 723891003 ps: (spi_device_scoreboard.sv:2236) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xf0ff72) != exp '{'{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h3c3fdc, wel:'h0, busy:'h0}, '{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h3c3fdc, wel:'h0, busy:'h0}}
  UVM_ERROR @ 724332867 ps: (spi_device_scoreboard.sv:2236) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xf0ff72) != exp '{'{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h3c3fdc, wel:'h0, busy:'h0}, '{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h3c3fdc, wel:'h0, busy:'h0}}
  UVM_ERROR @ 724588683 ps: (spi_device_scoreboard.sv:2236) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xf0ff72) != exp '{'{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h3c3fdc, wel:'h0, busy:'h0}, '{other_status:'h12588, wel:'h0, busy:'h0}, '{other_status:'h3c3fdc, wel:'h0, busy:'h0}}