SPI_DEVICE/2P Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.300m	264.540ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.590s	15.369us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.270s	188.851us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.040s	2.352ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.240s	12.154ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.420s	109.977us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.270s	188.851us	20	20	100.00
		spi_device_csr_aliasing	17.240s	12.154ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.240s	37.438us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.810s	70.524us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.400s	22.350us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.680s	26.902us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	2.220s	63.093us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.740s	1.001ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.740s	1.001ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.060s	8.719ms	50	50	100.00
		spi_device_tpm_sts_read	2.590s	84.385us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	44.520s	9.399ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.810s	32.122ms	50	50	100.00
		spi_device_flash_all	6.767m	290.876ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	41.080s	107.037ms	50	50	100.00
		spi_device_flash_all	6.767m	290.876ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	41.080s	107.037ms	50	50	100.00
		spi_device_flash_all	6.767m	290.876ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.767m	290.876ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.950s	3.733ms	50	50	100.00
		spi_device_flash_all	6.767m	290.876ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.950s	3.733ms	50	50	100.00
		spi_device_flash_all	6.767m	290.876ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.950s	3.733ms	50	50	100.00
		spi_device_flash_all	6.767m	290.876ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.950s	3.733ms	50	50	100.00
		spi_device_flash_all	6.767m	290.876ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.950s	3.733ms	50	50	100.00
		spi_device_flash_all	6.767m	290.876ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	41.800s	19.460ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.315m	37.821ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.315m	37.821ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.315m	37.821ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	49.810s	3.381ms	50	50	100.00
		spi_device_read_buffer_direct	16.080s	1.158ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.315m	37.821ms	50	50	100.00
		spi_device_flash_all	6.767m	290.876ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.767m	290.876ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.767m	290.876ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	18.130s	7.176ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	18.130s	7.176ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.300m	264.540ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.550m	76.105ms	50	50	100.00
V2	stress_all	spi_device_stress_all	26.713m	1.647s	50	50	100.00
V2	alert_test	spi_device_alert_test	2.280s	20.350us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.350s	14.429us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.450s	487.844us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.450s	487.844us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.590s	15.369us	5	5	100.00
		spi_device_csr_rw	4.270s	188.851us	20	20	100.00
		spi_device_csr_aliasing	17.240s	12.154ms	5	5	100.00
		spi_device_same_csr_outstanding	5.560s	63.491us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.590s	15.369us	5	5	100.00
		spi_device_csr_rw	4.270s	188.851us	20	20	100.00
		spi_device_csr_aliasing	17.240s	12.154ms	5	5	100.00
		spi_device_same_csr_outstanding	5.560s	63.491us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.620s	224.029us	5	5	100.00
		spi_device_tl_intg_err	19.570s	843.586us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.570s	843.586us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.070m	46.113ms	50	50	100.00
		TOTAL			1151	1151	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.34	99.17	96.60	74.78	89.36	98.47	95.74	99.26