SPI_HOST Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.533m	6.379ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	16.037us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	21.854us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	159.373us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	39.134us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	48.482us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	21.854us	20	20	100.00
		spi_host_csr_aliasing	5.000s	39.134us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	42.716us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	20.429us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	6.000s	299.987us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	39.000s	4.374ms	50	50	100.00
		spi_host_error_cmd	5.000s	42.023us	50	50	100.00
		spi_host_event	8.533m	15.381ms	50	50	100.00
V2	clock_rate	spi_host_speed	12.000s	863.570us	50	50	100.00
V2	speed	spi_host_speed	12.000s	863.570us	50	50	100.00
V2	chip_select_timing	spi_host_speed	12.000s	863.570us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	1.833m	4.248ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	30.465us	50	50	100.00
V2	cpol_cpha	spi_host_speed	12.000s	863.570us	50	50	100.00
V2	full_cycle	spi_host_speed	12.000s	863.570us	50	50	100.00
V2	duplex	spi_host_smoke	2.533m	6.379ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.533m	6.379ms	50	50	100.00
V2	stress_all	spi_host_stress_all	2.683m	27.320ms	50	50	100.00
V2	spien	spi_host_spien	7.150m	21.428ms	50	50	100.00
V2	stall	spi_host_status_stall	6.133m	11.335ms	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	49.000s	2.090ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	39.000s	4.374ms	50	50	100.00
V2	alert_test	spi_host_alert_test	5.000s	29.624us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	34.051us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	352.844us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	352.844us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	16.037us	5	5	100.00
		spi_host_csr_rw	5.000s	21.854us	20	20	100.00
		spi_host_csr_aliasing	5.000s	39.134us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	62.248us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	16.037us	5	5	100.00
		spi_host_csr_rw	5.000s	21.854us	20	20	100.00
		spi_host_csr_aliasing	5.000s	39.134us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	62.248us	20	20	100.00
V2		TOTAL			690	690	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	136.587us	20	20	100.00
		spi_host_sec_cm	5.000s	82.413us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	136.587us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	11.967m	36.585ms	9	10	90.00
		TOTAL			839	840	99.88

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.20	96.78	93.27	98.69	94.36	73.07	100.00	97.29	90.42

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.14187436178167592206147185004416880006356106241564864792966463109488864844026
      Line 112, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---