SRAM_CTRL/MAIN Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: `4a542c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.816m	2.184ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.040s	21.284us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.040s	24.975us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.120s	711.186us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.010s	98.611us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.640s	5.157ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.040s	24.975us	20	20	100.00
		sram_ctrl_csr_aliasing	2.010s	98.611us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.075m	20.881ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.902m	5.028ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	22.094m	32.886ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.288m	4.880ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	38.289m	320.912ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	27.438m	20.518ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.952m	61.082ms	50	50	100.00
V2	executable	sram_ctrl_executable	19.356m	55.174ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.874m	2.658ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.854m	31.417ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.411m	1.585ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.902m	791.167us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.799m	5.713ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	21.613m	19.733ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.750s	4.199ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.780h	251.291ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.160s	47.384us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.760s	146.319us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.760s	146.319us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.040s	21.284us	5	5	100.00
		sram_ctrl_csr_rw	2.040s	24.975us	20	20	100.00
		sram_ctrl_csr_aliasing	2.010s	98.611us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.080s	55.489us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.040s	21.284us	5	5	100.00
		sram_ctrl_csr_rw	2.040s	24.975us	20	20	100.00
		sram_ctrl_csr_aliasing	2.010s	98.611us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.080s	55.489us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	42.590s	14.158ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.890s	5.690us	0	5	0.00
		sram_ctrl_tl_intg_err	3.350s	373.520us	19	20	95.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.890s	5.690us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.350s	373.520us	19	20	95.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	21.613m	19.733ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	21.613m	19.733ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.040s	24.975us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	19.356m	55.174ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	19.356m	55.174ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	19.356m	55.174ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.952m	61.082ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	12.640s	11.042ms	42	50	84.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	42.590s	14.158ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	10.720s	2.760ms	42	50	84.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.816m	2.184ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.816m	2.184ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	19.356m	55.174ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.890s	5.690us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.952m	61.082ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.890s	5.690us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.890s	5.690us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.816m	2.184ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.890s	5.690us	0	5	0.00
V2S		TOTAL			123	145	84.83
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.892m	2.788ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1168	1190	98.15

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.08	99.11	93.01	85.46	100.00	98.03	98.61	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 8 failures:
- Test sram_ctrl_readback_err has 8 failures.
  - 5.sram_ctrl_readback_err.97061257562274038420485523291538558090100853699422016463078049960119914553449
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 2439004682 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6b) != exp (0x5c)
  UVM_INFO @ 2439004682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.sram_ctrl_readback_err.19608745425637663609222521532583302574342147553337263000787573534463074440849
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/6.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 2526171359 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x66) != exp (0x3b)
  UVM_INFO @ 2526171359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
Offending 'reqfifo_rvalid' has 7 failures:
- Test sram_ctrl_mubi_enc_err has 7 failures.
  - 8.sram_ctrl_mubi_enc_err.7286340017305302016501411346045939645981523712059287554528294724646317606130
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/8.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 690977326 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 690977326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.sram_ctrl_mubi_enc_err.38916731063212113970750478649619050169502469947353672879498009100341139984535
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/10.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 2051847396 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 2051847396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:

Test sram_ctrl_sec_cm has 4 failures.

0.sram_ctrl_sec_cm.114727213942942767196138545251788310075860285148353768595962782244462637855767
Line 96, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   5690035 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   5690035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.sram_ctrl_sec_cm.55008818801472700866660740676568967797407737978440155862099166402507146312894
Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   6584624 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   6584624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 1.sram_ctrl_sec_cm.51569970910382852373279857643701218081693080047183676245698653957467649528477
    Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   2106163 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2106163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_tl_intg_err has 1 failures.
  - 4.sram_ctrl_tl_intg_err.107089283656106478528878836153368997547854631704413919235152816747322276840598
    Line 307, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 220365970 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 220365970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5185) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_mubi_enc_err has 1 failures.

23.sram_ctrl_mubi_enc_err.13217578990855599052476142854300131556889456967984912463938283332260123439346
Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/23.sram_ctrl_mubi_enc_err/latest/run.log

  UVM_ERROR @ 697291018 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5185) { a_addr: 'h4baeacd8  a_data: 'h7a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h86  a_opcode: 'h1  a_user: 'h2566f  d_param: 'h0  d_source: 'h86  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 697291018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---