SRAM_CTRL/RET Simulation Results

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: 4a542c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.620m	1.005ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.020s	22.289us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.060s	12.866us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.400s	303.057us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.180s	74.247us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.460s	70.879us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.060s	12.866us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	74.247us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.360s	2.842ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	9.100s	2.732ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	21.438m	107.035ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.243m	38.348ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.721m	18.729ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	24.036m	5.424ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.810s	649.963us	50	50	100.00
V2	executable	sram_ctrl_executable	23.257m	31.769ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.656m	357.585us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.173m	54.228ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.666m	1.434ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.783m	287.909us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.703m	278.635us	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.843m	13.366ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.300s	42.156us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.261h	369.898ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.120s	11.219us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.700s	338.074us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.700s	338.074us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.020s	22.289us	5	5	100.00
		sram_ctrl_csr_rw	2.060s	12.866us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	74.247us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.180s	32.093us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.020s	22.289us	5	5	100.00
		sram_ctrl_csr_rw	2.060s	12.866us	20	20	100.00
		sram_ctrl_csr_aliasing	2.180s	74.247us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.180s	32.093us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.980s	1.691ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.090s	5.606us	0	5	0.00
		sram_ctrl_tl_intg_err	5.720s	2.968ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.090s	5.606us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	5.720s	2.968ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.843m	13.366ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.843m	13.366ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.060s	12.866us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.257m	31.769ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.257m	31.769ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.257m	31.769ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.810s	649.963us	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.610s	44.796us	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.980s	1.691ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.590s	40.350us	41	50	82.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.620m	1.005ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.620m	1.005ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.257m	31.769ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.090s	5.606us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.810s	649.963us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.090s	5.606us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.090s	5.606us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.620m	1.005ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.090s	5.606us	0	5	0.00
V2S		TOTAL			126	145	86.90
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	10.220m	5.951ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1169	1190	98.24

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.05	99.07	93.01	85.37	100.00	97.99	98.60	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 9 failures:

  • Test sram_ctrl_readback_err has 9 failures.

    • 0.sram_ctrl_readback_err.55493879194913941252881465879861526982090723392111670238443231578082415768054
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 118980698 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x31) != exp (0x62)
        UVM_INFO @ 118980698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 9.sram_ctrl_readback_err.35853220168593785022857563775162695247241270090401691489843777490933766467951
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  53525943 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x39) != exp (0x5d)
        UVM_INFO @  53525943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• Offending 'reqfifo_rvalid' has 5 failures:

  • Test sram_ctrl_mubi_enc_err has 5 failures.

    • 5.sram_ctrl_mubi_enc_err.99534423949638246606170997711997439120256030062948460805590923881602047436244
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  23565680 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  23565680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 13.sram_ctrl_mubi_enc_err.101331556207179785333639767098077092998735410055035629135392865135697068336443
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 396282380 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 396282380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 2.sram_ctrl_sec_cm.64028462834042727619496607568177536474578031964968048492491510968069340277943
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   5817100 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   5817100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.115647906480207517362409800043975547604490131007277832254549471293870025224192
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7338968 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7338968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.62398105039511506839220717400354337977583253858174325444628356331395570294714
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   4639808 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   4639808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.91779094683222621051506868024118423202541862687645286425562060964083464963173
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  11132808 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  11132808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 13.sram_ctrl_csr_mem_rw_with_rand_reset.68595429841073660544546901768388237498745807962301625910140829019473157357914
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  23961055 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
        UVM_INFO @  23961055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 14.sram_ctrl_csr_mem_rw_with_rand_reset.33049270447965118614998218098856329481005965382540553124366784400062419892940
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 100438202 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @ 100438202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---