ADC_CTRL Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: 6adf14f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	21.660s	6.070ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.520s	1.048ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.710s	469.963us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.596m	52.752ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.740s	1.168ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.760s	585.303us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.710s	469.963us	20	20	100.00
		adc_ctrl_csr_aliasing	4.740s	1.168ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	21.795m	491.272ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	23.721m	487.121ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.172m	485.698ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.510m	490.620ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	25.157m	546.619ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.225m	619.682ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	30.860m	593.120ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.481m	517.024ms	34	50	68.00
V2	poweron_counter	adc_ctrl_poweron_counter	17.390s	5.106ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.179m	41.194ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	8.052m	141.966ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	55.914m	4.032s	49	50	98.00
V2	alert_test	adc_ctrl_alert_test	2.560s	526.702us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.710s	530.495us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.860s	415.818us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.860s	415.818us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.520s	1.048ms	5	5	100.00
		adc_ctrl_csr_rw	2.710s	469.963us	20	20	100.00
		adc_ctrl_csr_aliasing	4.740s	1.168ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.280s	4.950ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.520s	1.048ms	5	5	100.00
		adc_ctrl_csr_rw	2.710s	469.963us	20	20	100.00
		adc_ctrl_csr_aliasing	4.740s	1.168ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.280s	4.950ms	20	20	100.00
V2		TOTAL			723	740	97.70
V2S	tl_intg_err	adc_ctrl_sec_cm	25.320s	8.068ms	5	5	100.00
		adc_ctrl_tl_intg_err	17.620s	8.239ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	17.620s	8.239ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	33.030s	40.887ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			900	920	97.83

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.41	99.05	96.03	100.00	100.00	98.64	97.57	90.56

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 10 failures:
  • Test adc_ctrl_clock_gating has 10 failures.

    • 0.adc_ctrl_clock_gating.99304048006409799509706611259440913446256750011335275258145003023885642250006
      Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 9.adc_ctrl_clock_gating.78092106183854415199577196681748807628714084575216260779979790256695760620690
      Line 182, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 10 failures:

  • Test adc_ctrl_clock_gating has 6 failures.

    • 3.adc_ctrl_clock_gating.64835732830115440269428153961474320160077826037379299229551180867976494734964
      Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 4524809484 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 4524809484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.adc_ctrl_clock_gating.76456242337895378785760797639028466841696863699409749849531779195586683907600
      Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 175386396023 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 175386396023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

  • Test adc_ctrl_stress_all has 1 failures.

    • 9.adc_ctrl_stress_all.66342630330202028344949109238862878843290083373465243122499031487266376072935
      Line 149, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3535812712 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 3535812712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test adc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 18.adc_ctrl_stress_all_with_rand_reset.39854551774257996766309682598625559988123110222957551731946142419032125769653
      Line 167, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5405291016 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 5405291016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 36.adc_ctrl_stress_all_with_rand_reset.94539740572391435602168932375353683888265959551118475552283632510643307332332
      Line 182, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9294724593 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 9294724593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.