AES/MASKED Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: `6adf14f`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	120.679us	1	1	100.00
V1	smoke	aes_smoke	11.000s	491.425us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	12.000s	60.729us	5	5	100.00
V1	csr_rw	aes_csr_rw	12.000s	52.552us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	20.000s	3.052ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	14.000s	612.833us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	12.000s	120.905us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	12.000s	52.552us	20	20	100.00
		aes_csr_aliasing	14.000s	612.833us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	491.425us	50	50	100.00
		aes_config_error	18.000s	1.171ms	50	50	100.00
		aes_stress	1.267m	15.193ms	50	50	100.00
V2	key_length	aes_smoke	11.000s	491.425us	50	50	100.00
		aes_config_error	18.000s	1.171ms	50	50	100.00
		aes_stress	1.267m	15.193ms	50	50	100.00
V2	back2back	aes_stress	1.267m	15.193ms	50	50	100.00
		aes_b2b	37.000s	718.046us	50	50	100.00
V2	backpressure	aes_stress	1.267m	15.193ms	50	50	100.00
V2	multi_message	aes_smoke	11.000s	491.425us	50	50	100.00
		aes_config_error	18.000s	1.171ms	50	50	100.00
		aes_stress	1.267m	15.193ms	50	50	100.00
		aes_alert_reset	10.000s	2.086ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	7.000s	289.564us	50	50	100.00
		aes_config_error	18.000s	1.171ms	50	50	100.00
		aes_alert_reset	10.000s	2.086ms	50	50	100.00
V2	trigger_clear_test	aes_clear	28.000s	2.385ms	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	16.000s	265.796us	1	1	100.00
V2	reset_recovery	aes_alert_reset	10.000s	2.086ms	50	50	100.00
V2	stress	aes_stress	1.267m	15.193ms	50	50	100.00
V2	sideload	aes_stress	1.267m	15.193ms	50	50	100.00
		aes_sideload	8.000s	287.745us	50	50	100.00
V2	deinitialization	aes_deinit	7.000s	167.750us	50	50	100.00
V2	stress_all	aes_stress_all	1.400m	8.324ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	56.933us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	13.000s	76.352us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	13.000s	76.352us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	12.000s	60.729us	5	5	100.00
		aes_csr_rw	12.000s	52.552us	20	20	100.00
		aes_csr_aliasing	14.000s	612.833us	5	5	100.00
		aes_same_csr_outstanding	12.000s	139.850us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	12.000s	60.729us	5	5	100.00
		aes_csr_rw	12.000s	52.552us	20	20	100.00
		aes_csr_aliasing	14.000s	612.833us	5	5	100.00
		aes_same_csr_outstanding	12.000s	139.850us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	15.000s	575.484us	50	50	100.00
V2S	fault_inject	aes_fi	37.000s	2.670ms	49	50	98.00
		aes_control_fi	56.000s	10.003ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	12.000s	131.843us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	12.000s	131.843us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	12.000s	131.843us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	12.000s	131.843us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	80.887us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	917.952us	5	5	100.00
		aes_tl_intg_err	13.000s	643.300us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	13.000s	643.300us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	2.086ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	12.000s	131.843us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	491.425us	50	50	100.00
		aes_stress	1.267m	15.193ms	50	50	100.00
		aes_alert_reset	10.000s	2.086ms	50	50	100.00
		aes_core_fi	1.033m	10.005ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	12.000s	131.843us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	85.711us	50	50	100.00
		aes_stress	1.267m	15.193ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.267m	15.193ms	50	50	100.00
		aes_sideload	8.000s	287.745us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	85.711us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	85.711us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	85.711us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	85.711us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	85.711us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.267m	15.193ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.267m	15.193ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	37.000s	2.670ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	37.000s	2.670ms	49	50	98.00
		aes_control_fi	56.000s	10.003ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	340	350	97.14
		aes_ctr_fi	5.000s	178.920us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	37.000s	2.670ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	37.000s	2.670ms	49	50	98.00
		aes_control_fi	56.000s	10.003ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.006ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	37.000s	2.670ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	37.000s	2.670ms	49	50	98.00
		aes_control_fi	56.000s	10.003ms	284	300	94.67
		aes_ctr_fi	5.000s	178.920us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	37.000s	2.670ms	49	50	98.00
		aes_control_fi	56.000s	10.003ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	340	350	97.14
		aes_ctr_fi	5.000s	178.920us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	2.086ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	37.000s	2.670ms	49	50	98.00
		aes_control_fi	56.000s	10.003ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	340	350	97.14
		aes_ctr_fi	5.000s	178.920us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	37.000s	2.670ms	49	50	98.00
		aes_control_fi	56.000s	10.003ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	340	350	97.14
		aes_ctr_fi	5.000s	178.920us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	37.000s	2.670ms	49	50	98.00
		aes_control_fi	56.000s	10.003ms	284	300	94.67
		aes_ctr_fi	5.000s	178.920us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	37.000s	2.670ms	49	50	98.00
		aes_control_fi	56.000s	10.003ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	340	350	97.14
V2S		TOTAL			957	985	97.16
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	31.000s	2.477ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1563	1602	97.57

Failure Buckets

Job timed out after * minutes has 12 failures:
- Test aes_control_fi has 9 failures.
  - 37.aes_control_fi.29138438228389211804463839743057972279039109342447391591201889253454579185901
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/37.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 79.aes_control_fi.58571977606217792125125401356733042910804975677741234564439693297768954496878
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/79.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.
- Test aes_cipher_fi has 3 failures.
  - 128.aes_cipher_fi.27016126498431040579353590369728156152136566595436615027341363460197854922952
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/128.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 182.aes_cipher_fi.49349871817102331215279119437371989549227528653040350154386172346418019275889
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/182.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 1 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 4.aes_cipher_fi.66951140362342738072164845266516327715635986984874295724176789196143037984708
    Line 141, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10046020918 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10046020918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 122.aes_cipher_fi.78100131670313080190143600568353089649621858038112945068069390922255755321781
    Line 139, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/122.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014816717 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014816717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 11.aes_control_fi.66902375728950978594549494663626816317201484042904611534212468004384155921218
    Line 133, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10019594092 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019594092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 13.aes_control_fi.83038595891563575276715299034515060747014719413730725747095244316386482386476
    Line 142, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10028592601 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028592601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.53908240027731407594980353317194715848721010053424411346978855648309892762693
Line 406, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 269474752 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 269474752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.585368217537311367327239101063600267039032147489040011855166963072344709957
Line 763, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2476555051 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2476555051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.112685474051226613958419277966193862295773723790250090677926769113982725759580
    Line 161, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 124954129 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 124954129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

5.aes_fi.99498188979406595283648374133551634687449447699382066435620324811425372856566
Line 2919, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 32375410 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 32342077 PS)
  UVM_ERROR @  32375410 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  32375410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:946) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.73070210709801821118241061985086301877258380350771258894780585440853463224683
    Line 166, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 607107477 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 607107477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.115758870237286276254823604052768738280882757382386102603076033320114416161806
    Line 338, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 945374632 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 945374632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.76333135923982242701671436032327119951312878452350001619398573996785018767184
    Line 362, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 238808896 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 238808896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 43.aes_core_fi.81188198448520105469992758271989403208492782430864511833210099028169495989552
    Line 143, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/43.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004791264 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004791264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 45.aes_clear.6505244716178187127581932119967155086506340484373127947280442402167717027726
    Line 1305, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/45.aes_clear/latest/run.log
```
  UVM_FATAL @  31467302 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
           TEST FAILED MESSAGES DID NOT MATCH

                 0 7d 	 29 	 23 	 0
                 1 38 	 d7 	 89 	 0
```

Job returned non-zero exit code has 1 failures:

Test aes has 1 failures.

cov_merge
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_merge/merged/cov_merge.log

  [Executing]:
  make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'

  [make]: cov_merge
  imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
  *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
  Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
  Created log file /nightly/current_run/opentitan/startup.log
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1

Job killed most likely because its dependent job failed. has 1 failures:
- Test aes has 1 failures.
  - cov_report
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_report/cov_report.log