AES/UNMASKED Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: `6adf14f`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	94.400us	1	1	100.00
V1	smoke	aes_smoke	5.000s	92.199us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	31.000s	58.430us	5	5	100.00
V1	csr_rw	aes_csr_rw	32.000s	85.402us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	35.000s	591.849us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	32.000s	101.152us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	30.000s	198.682us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	32.000s	85.402us	20	20	100.00
		aes_csr_aliasing	32.000s	101.152us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	92.199us	50	50	100.00
		aes_config_error	5.000s	157.703us	50	50	100.00
		aes_stress	5.000s	401.776us	50	50	100.00
V2	key_length	aes_smoke	5.000s	92.199us	50	50	100.00
		aes_config_error	5.000s	157.703us	50	50	100.00
		aes_stress	5.000s	401.776us	50	50	100.00
V2	back2back	aes_stress	5.000s	401.776us	50	50	100.00
		aes_b2b	8.000s	423.655us	50	50	100.00
V2	backpressure	aes_stress	5.000s	401.776us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	92.199us	50	50	100.00
		aes_config_error	5.000s	157.703us	50	50	100.00
		aes_stress	5.000s	401.776us	50	50	100.00
		aes_alert_reset	5.000s	911.935us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	62.048us	50	50	100.00
		aes_config_error	5.000s	157.703us	50	50	100.00
		aes_alert_reset	5.000s	911.935us	50	50	100.00
V2	trigger_clear_test	aes_clear	5.000s	83.707us	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	242.891us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	911.935us	50	50	100.00
V2	stress	aes_stress	5.000s	401.776us	50	50	100.00
V2	sideload	aes_stress	5.000s	401.776us	50	50	100.00
		aes_sideload	7.000s	271.538us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	301.872us	50	50	100.00
V2	stress_all	aes_stress_all	23.000s	1.835ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	52.026us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	33.000s	295.389us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	33.000s	295.389us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	31.000s	58.430us	5	5	100.00
		aes_csr_rw	32.000s	85.402us	20	20	100.00
		aes_csr_aliasing	32.000s	101.152us	5	5	100.00
		aes_same_csr_outstanding	31.000s	67.645us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	31.000s	58.430us	5	5	100.00
		aes_csr_rw	32.000s	85.402us	20	20	100.00
		aes_csr_aliasing	32.000s	101.152us	5	5	100.00
		aes_same_csr_outstanding	31.000s	67.645us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	5.000s	192.164us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	170.195us	50	50	100.00
		aes_control_fi	45.000s	10.002ms	280	300	93.33
		aes_cipher_fi	40.000s	10.003ms	332	350	94.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	31.000s	145.454us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	31.000s	145.454us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	31.000s	145.454us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	31.000s	145.454us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	32.000s	157.959us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	607.903us	5	5	100.00
		aes_tl_intg_err	33.000s	305.703us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	33.000s	305.703us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	911.935us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	31.000s	145.454us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	92.199us	50	50	100.00
		aes_stress	5.000s	401.776us	50	50	100.00
		aes_alert_reset	5.000s	911.935us	50	50	100.00
		aes_core_fi	4.600m	10.009ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	31.000s	145.454us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	79.658us	50	50	100.00
		aes_stress	5.000s	401.776us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	401.776us	50	50	100.00
		aes_sideload	7.000s	271.538us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	79.658us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	79.658us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	79.658us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	79.658us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	79.658us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	401.776us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	401.776us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	170.195us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	170.195us	50	50	100.00
		aes_control_fi	45.000s	10.002ms	280	300	93.33
		aes_cipher_fi	40.000s	10.003ms	332	350	94.86
		aes_ctr_fi	4.000s	52.754us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	170.195us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	170.195us	50	50	100.00
		aes_control_fi	45.000s	10.002ms	280	300	93.33
		aes_cipher_fi	40.000s	10.003ms	332	350	94.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	40.000s	10.003ms	332	350	94.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	170.195us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	170.195us	50	50	100.00
		aes_control_fi	45.000s	10.002ms	280	300	93.33
		aes_ctr_fi	4.000s	52.754us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	170.195us	50	50	100.00
		aes_control_fi	45.000s	10.002ms	280	300	93.33
		aes_cipher_fi	40.000s	10.003ms	332	350	94.86
		aes_ctr_fi	4.000s	52.754us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	911.935us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	170.195us	50	50	100.00
		aes_control_fi	45.000s	10.002ms	280	300	93.33
		aes_cipher_fi	40.000s	10.003ms	332	350	94.86
		aes_ctr_fi	4.000s	52.754us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	170.195us	50	50	100.00
		aes_control_fi	45.000s	10.002ms	280	300	93.33
		aes_cipher_fi	40.000s	10.003ms	332	350	94.86
		aes_ctr_fi	4.000s	52.754us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	170.195us	50	50	100.00
		aes_control_fi	45.000s	10.002ms	280	300	93.33
		aes_ctr_fi	4.000s	52.754us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	170.195us	50	50	100.00
		aes_control_fi	45.000s	10.002ms	280	300	93.33
		aes_cipher_fi	40.000s	10.003ms	332	350	94.86
V2S		TOTAL			942	985	95.63
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	25.000s	760.884us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1548	1602	96.63

Failure Buckets

Job timed out after * minutes has 27 failures:
- Test aes_control_fi has 12 failures.
  - 6.aes_control_fi.96529248380193319444097420800318156381102217621909134927658300705402407203875
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 29.aes_control_fi.104060046868797675080341718851752861892638237302861805590463596524922728269457
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 15 failures.
  - 11.aes_cipher_fi.58828245807058741986228411902931930858195885811321999997367914229173400792347
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 13.aes_cipher_fi.69303592793572286737827034823521322088116599432732657110573276016570599885916
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 51.aes_control_fi.51282515097782110061101468609572002807752731273558390859205185001452967023752
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/51.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005098502 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005098502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 54.aes_control_fi.79870530876217294570293828648665381125837052843718918483576383311061584808476
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/54.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002100562 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002100562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.64174024787036398521139857818093920456006092951836353704122177703798484157794
Line 904, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 919901522 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 919901522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.34308369745213991401173583967481533720851480337688837725785067533167201672453
Line 375, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1001323539 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1001323539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 72.aes_cipher_fi.73520667498345831222550224218468286335821408443230087431991232232606605909552
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/72.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015010348 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015010348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 175.aes_cipher_fi.83353752074379730825009851377782965310106204827003859978031206819300955993749
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/175.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003008227 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003008227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 8.aes_core_fi.101617771223832720987667814891191115568229309049466184471579774620907595215428
    Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008947106 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008947106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 51.aes_core_fi.84810983974771143784777208277432971847525389044670871726512407039708536624302
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/51.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008176526 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008176526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:

Test aes_core_fi has 2 failures.

35.aes_core_fi.43517861335634570531917722100398513589154929188545948625398331611758768490921
Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/35.aes_core_fi/latest/run.log

  UVM_FATAL @ 10053482050 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x219e1184, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10053482050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

67.aes_core_fi.67486747005843454509461893313178175869317827901451461341105092599033434380037
Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/67.aes_core_fi/latest/run.log

  UVM_FATAL @ 10009051043 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x43f66384, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10009051043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.104169942790091531136133815328919457703840559765237582659714430818912858150267
    Line 860, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3561917784 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 3561917784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.738704812842359535496013664357390445193627245910662546035099299406385430892
    Line 162, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  95695053 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  95695053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:946) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.1443727958104861075722538710046461143481096481069690099803956967429901838162
    Line 175, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 760883573 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 760883573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:714) scoreboard [scoreboard] has 1 failures:
- Test aes_clear has 1 failures.
  - 49.aes_clear.34170008774899932177436228407911922354214481844598717732529782316194769756253
    Line 8371, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/49.aes_clear/latest/run.log
```
  UVM_FATAL @  88253262 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       ----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
       ----| Expected:           5
       ----| Seen:               6
       ----| Expected corrupted: 0
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 62.aes_core_fi.21908923434717905078448668973516610868885716354480777051604622799740275595193
    Line 142, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/62.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010565599 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010565599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 1 failures:

Test aes has 1 failures.

cov_merge
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/cov_merge/merged/cov_merge.log

  [Executing]:
  make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'

  [make]: cov_merge
  imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
  *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
  Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
  Created log file /nightly/current_run/opentitan/startup.log
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1

Job killed most likely because its dependent job failed. has 1 failures:
- Test aes has 1 failures.
  - cov_report
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/cov_report/cov_report.log