CSRNG Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: 6adf14f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 7.000s 246.619us 50 50 100.00
V1 csr_hw_reset csrng_csr_hw_reset 4.000s 26.790us 5 5 100.00
V1 csr_rw csrng_csr_rw 4.000s 20.675us 20 20 100.00
V1 csr_bit_bash csrng_csr_bit_bash 14.000s 533.040us 5 5 100.00
V1 csr_aliasing csrng_csr_aliasing 7.000s 258.087us 5 5 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 5.000s 85.954us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 4.000s 20.675us 20 20 100.00
csrng_csr_aliasing 7.000s 258.087us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 interrupts csrng_intr 18.000s 734.176us 176 200 88.00
V2 alerts csrng_alert 1.800m 8.032ms 500 500 100.00
V2 err csrng_err 5.000s 28.087us 463 500 92.60
V2 cmds csrng_cmds 11.500m 60.250ms 50 50 100.00
V2 life cycle csrng_cmds 11.500m 60.250ms 50 50 100.00
V2 stress_all csrng_stress_all 24.967m 100.281ms 47 50 94.00
V2 intr_test csrng_intr_test 4.000s 49.719us 50 50 100.00
V2 alert_test csrng_alert_test 6.000s 158.298us 50 50 100.00
V2 tl_d_oob_addr_access csrng_tl_errors 9.000s 143.409us 20 20 100.00
V2 tl_d_illegal_access csrng_tl_errors 9.000s 143.409us 20 20 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 4.000s 26.790us 5 5 100.00
csrng_csr_rw 4.000s 20.675us 20 20 100.00
csrng_csr_aliasing 7.000s 258.087us 5 5 100.00
csrng_same_csr_outstanding 8.000s 210.972us 20 20 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 4.000s 26.790us 5 5 100.00
csrng_csr_rw 4.000s 20.675us 20 20 100.00
csrng_csr_aliasing 7.000s 258.087us 5 5 100.00
csrng_same_csr_outstanding 8.000s 210.972us 20 20 100.00
V2 TOTAL 1376 1440 95.56
V2S tl_intg_err csrng_sec_cm 8.000s 257.142us 5 5 100.00
csrng_tl_intg_err 17.000s 1.369ms 20 20 100.00
V2S sec_cm_config_regwen csrng_regwen 5.000s 158.452us 50 50 100.00
csrng_csr_rw 4.000s 20.675us 20 20 100.00
V2S sec_cm_config_mubi csrng_alert 1.800m 8.032ms 500 500 100.00
V2S sec_cm_intersig_mubi csrng_stress_all 24.967m 100.281ms 47 50 94.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
csrng_sec_cm 8.000s 257.142us 5 5 100.00
V2S sec_cm_update_fsm_sparse csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
csrng_sec_cm 8.000s 257.142us 5 5 100.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
csrng_sec_cm 8.000s 257.142us 5 5 100.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
csrng_sec_cm 8.000s 257.142us 5 5 100.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
csrng_sec_cm 8.000s 257.142us 5 5 100.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
csrng_sec_cm 8.000s 257.142us 5 5 100.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
csrng_sec_cm 8.000s 257.142us 5 5 100.00
V2S sec_cm_ctrl_mubi csrng_alert 1.800m 8.032ms 500 500 100.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
V2S sec_cm_constants_lc_gated csrng_stress_all 24.967m 100.281ms 47 50 94.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 1.800m 8.032ms 500 500 100.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 17.000s 1.369ms 20 20 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
csrng_sec_cm 8.000s 257.142us 5 5 100.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
csrng_sec_cm 8.000s 257.142us 5 5 100.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 18.000s 734.176us 176 200 88.00
csrng_err 5.000s 28.087us 463 500 92.60
V2S TOTAL 75 75 100.00
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 6.133m 24.307ms 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 1566 1630 96.07

Failure Buckets